Abstract: A delay circuit includes a memory addresses of which is designated by a counter incremented in response to each clock signal from an initial value set by an initial value setting circuit to an end value. A digital signal is written into an address as designated and read and converted into an analog signal to be outputted at an output terminal through a buffer amplifier. A delay time is determined by the writing timing and the reading timing of the digital signal. If the delay time is to be varied in the course of a delaying operation, a further initial value is set in the counter.

Abstract: A logarithmic amplification circuit is provided with a first transistor 10 having its collector supplied with a first input current, a second transistor 11 having its collector supplied with a second input current and being differentially connected to the first transistor, a comparing circuit 13 for receiving the first and second input currents to supply a signal corresponding to a difference between the two input currents to a base of the second transistor, and first and second constant current circuits 21 and 25 for supplying respective collectors of the first and the second transistors with equivalent compensating current. An output voltage corresponding to a difference between a logarithmically amplified value of the first input current and a logarithmically amplified value of the second input current can be obtained.

Abstract: A signal distinction circuit comprising a noise detector for detecting a noise included in a received signal; and a maintaining circuit for maintaining the condition of a signal outputted from a detector for detecting a discrimination signal according to a signal outputted from the noise detector so that since the noise detector and the maintaining circuit prevent the condition of a signal outputted from the distinction circuit from being changed when an inteference such as a multipath interference occuurs, an output corresponding to a received signal can be reliably obtained.

Abstract: A television receiver includes a volume control circuit (4) for controlling levels of sound signals corresponding to a left channel, a right channel, a center channel and a surround channel and speakers (6 to 10) corresponding to these channels. The television receiver further comprises a test tone circuit (11; 18), a microcomputer (14) and a character display circuit (16). The test tone circuit (11; 18) supplies a test tone of a prescribed frequency sequentially to the speakers (6 to 10) through the volume control circuit (4). The microcomputer (14) provides a command to the character display circuit (16) so that a CRT 17) displays which speaker is currently supplied with the test tone as well as volume levels of the respective speakers.

Abstract: An FM receiver includes a first antenna and a second antenna. A first pulse generator produces a first pulse according to a noise signal included in the signal received by the first antennas, and a second pulse generator produces a second pulse according to a noise signal included in the signal received by the second antennas. A calculation circuit including shift registers is provided for shifting data, which is either one of the first and second pulses, in one direction in accordance with the first pulse from the first pulse generator and for shifting the switch data in another direction in accordance with the second pulse from the second pulse generator. Also, a switch circuit is provided for switching on a transmission line for a signal received at either one of the first and second antenna in response to the data produced from the calculation circuit.

Abstract: A signal distinction circuit comprises a clock signal generating circuit for generating a clock signal whose frequency is longer than that of a pulse signal corresponding to a discrimination signal applied to a counter as an actuating signal; and an arithmetic circuit for operating the pulse signal and the clock signal, and generating an output signal according to the presence or non-presence of the discrimination signal so as to forcibly drive a detecting circuit to which an output signal of the counter is applied, whereby the detecting circuit can be forcibly driven irrespective of the condition of the counter when the discrimination signal is not applied thereto.

Abstract: A surround-decoder comprises terminals to which left and right stereo input signals are applied, a decoder for processing the left and the right stereo input signals to provide left and right stereo output signals, a center output signal and a surround output signal, circuits for detecting the left and the right stereo input signals to be monaural signals, and a switch responsive to an output signal of the detecting circuit for cutting off an output of a surround signal from the decoder.