Patents by Inventor Masayo Yamaki

Masayo Yamaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6446213
    Abstract: Before a register provided exclusively for an Advanced Configuration and Power Interface (ACPI) is set, a System Management Interrupt (SMI) is issued to a Central Processing Unit (CPU). A System Management-Basic Input Output System (SM-BIOS) performs the power management of a computer system. Values representing a wakeup factor of the system and a power management event are set in the register, and an Operating System Directed Power Management System (OSPM) is informed of a Power Management Event (PME). When the values are set in the register, an SMI is issued to the CPU, and the SM-BIOS performs the power management of the computer system.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: September 3, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masayo Yamaki
  • Patent number: 6282645
    Abstract: When a BIOS driver call request is generated in an environment of an OS operating in a protect mode, an IN or OUT instruction is executed to cause an I/O trap SMI generator to generate an I/O trap SMI. The mode of a CPU is switched from the protect mode to an SMM in accordance with the I/O trap SMI. In the SMM, the BIOS driver is executed. When the process of the BIOS driver is completed, the mode of the CPU is returned from the SMM to the protect mode, thereby shifting control to the OS. The BIOS can be directly called in the protect mode without building a routine for switching the CPU operating mode in the OS or application program operating in the protect mode.
    Type: Grant
    Filed: February 18, 1998
    Date of Patent: August 28, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masayo Yamaki
  • Patent number: 6230279
    Abstract: When a user instructs acceleration or deceleration of the CPU processing speed with an “accelerator” button or a “brake” button, a speed control MMI informs power management system software of the corresponding information to change the CPU processing speed. The change is recorded on a speed management database in correspondence with the name of the application program which is currently being executed. Every time acceleration or deceleration of the CPU processing speed is instructed by the user, speed management data is formed on the speed management database. By using the speed management data, the CPU processing speed can be dynamically controlled for each piece of software when it is executed. Further disclosed is a novel power dissipation control system for a microprocessor, adapted to be used in conjunction with the above described MMI.
    Type: Grant
    Filed: May 3, 2000
    Date of Patent: May 8, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Dewa, Masayo Yamaki, Fumitaka Sato
  • Patent number: 6081901
    Abstract: When a user instructs acceleration or deceleration of the CPU processing speed with an "accelerator" button or a "brake" button, a speed control MMI informs power management system software of the corresponding information to change the CPU processing speed. The change is recorded on a speed management database in correspondence with the name of the application program which is currently being executed. Every time acceleration or deceleration of the CPU processing speed is instructed by the user, speed management data is formed on the speed management database. By using the speed management data, the CPU processing speed can be dynamically controlled for each piece of software when it is executed. Further disclosed is a novel power dissipation control system for a microprocessor, adapted to be used in conjunction with the above described MMI.
    Type: Grant
    Filed: May 7, 1998
    Date of Patent: June 27, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Dewa, Masayo Yamaki, Fumitaka Sato
  • Patent number: 6016548
    Abstract: A computer system capable of entering a sleep mode is disclosed. The rate at which the computer switches between a normal state and a stop grant state while in the sleep mode is controllable by a timer. The stop grant state is an intermediate power consumption state between the sleep mode and the normal state. The timer may include a software system management interrupt timer. The system may also include processing to determine the cause of the switch from the stop grant state to the normal state.
    Type: Grant
    Filed: July 15, 1997
    Date of Patent: January 18, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobutaka Nakamura, Masayo Yamaki
  • Patent number: 5995454
    Abstract: When the user specifies the hours, minutes at which the system is to be started automatically, the year, month, day-of-month that the system is to be started automatically is determined by determining whether or not the specified hours, minutes has already passed the actual hours, minutes at the point in time at which the user specified the time. The determined year, month, day-of-month and the hours, minutes specified by the user are stored in a nonvolatile memory. In an RTC device, at least the hours, minutes of the year, month, day-of-month, hours, minutes stored in the memory can be set. When the actual hours, minutes has reached the set hours, minutes, the RTC device generates an alarm. When the RTC has generated an alarm, it is judged whether or not the actual year, month, day-of-month, hours, minutes at the point in time at which the alarm was generated coincides with the year, month, day-of-month, hours, minutes stored in the memory.
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: November 30, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masayo Yamaki
  • Patent number: 5963738
    Abstract: When a BIOS driver call request is generated in an environment of an OS operating in a protect mode, an IN or OUT instruction is executed to cause an I/O trap SMI generator to generate an I/O trap SMI. The mode of a CPU is switched from the protect mode to an SMM in accordance with the I/O trap SMI. In the SMM, the BIOS driver is executed. When the process of the BIOS driver is completed, the mode of the CPU is returned from the SMM to the protect mode, thereby shifting control to the OS. The BIOS can be directly called in the protect mode without building a routine for switching the CPU operating mode in the OS or application program operating in the protect mode.
    Type: Grant
    Filed: January 27, 1997
    Date of Patent: October 5, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayo Yamaki, Hiroyuki Tsukada
  • Patent number: 5931948
    Abstract: A portable computer system includes a keyboard for inputting at least a password, and a main CPU for controlling the system operation to perform a data processing. Particularly, the computer system further includes a password control section, holding one or more registered passwords as being unreadable by direct access from the main CPU, for allowing the main CPU to perform the data processing when a password identical to one of the registered passwords held therein is input by the keyboard.
    Type: Grant
    Filed: September 11, 1997
    Date of Patent: August 3, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshikazu Morisawa, Masayo Yamaki, Hiroyuki Tsukada, Tohru Mamata, Tatsuya Kawawa
  • Patent number: 5537544
    Abstract: A portable computer system includes a keyboard for inputting at least a password, and a main CPU for controlling the system operation to perform a data processing. Particularly, the computer system further includes a password control section, holding one or more registered passwords as being unreadable by direct access from the main CPU, for allowing the main CPU to perform the data processing when a password identical to one of the registered passwords held therein is input by the keyboard.
    Type: Grant
    Filed: August 16, 1993
    Date of Patent: July 16, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshikazu Morisawa, Masayo Yamaki, Hiroyuki Tsukada, Tohru Mamata, Tatsuya Kawawa
  • Patent number: 5485622
    Abstract: A CPU determines whether a password canceller is connected to a system main body prior to execution of password check processing on the basis of stored password information at the start of the system. When the password canceller is connected to the system main body, the CPU clears the stored password information to start the system. However, when the password canceller is not connected to system main body, the CPU executes password check processing and controls the start of the system.
    Type: Grant
    Filed: September 25, 1992
    Date of Patent: January 16, 1996
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Masayo Yamaki