Abstract: A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a memory element and a transistor are connected in series between data lines, a memory element and a transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data. A current application circuit has a function of adjusting current values flowing in data lines, and adjusts connection weight coefficients without rewriting the memory elements.

Abstract: A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a non-volatile semiconductor memory element and a cell transistor are connected in series between data lines, a non-volatile semiconductor memory element and a cell transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the non-volatile semiconductor memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data.

Abstract: Connection weight coefficients to be used in a neural network computation are stored in a memory array. A word line drive circuit drives a word line corresponding to input data of a neural network. A column selection circuit connects to a computation circuit bit lines to which a connection weight coefficient to be computed is connected. The computation circuit determines the sum of cell currents flowing in the bit lines. A result of the determination made by the computation circuit is stored in an output holding circuit, and is set as an input of a neural network in the next layer, to the word line drive circuit. A control circuit instructs the word line drive circuit and the column selection circuit to select the word line and the bit line to be used in the neural network computation, based on information held in a network configuration information holding circuit.

Abstract: A neural network computation circuit includes in-area multiple-word line selection circuits that are provided in one-to-one correspondence to a plurality of word line areas into which a plurality of word lines included in a memory array are logically divided. Each of the in-area multiple-word line selection circuits sets one or more word lines in a selected state or a non-selected state, and includes a first latch and a second latch provided for each word line.

Abstract: The purpose of the present invention is to provide a breeding method for a plant having a blue flower color with a simpler blue color development controlling technique, without requiring complex mechanisms for blue color development that have been previously presented and techniques reproducing such mechanisms. Delphinidin-based anthocyanins, in which the both 3? and 5?-positions of the anthocyanin B-ring have been glycosylated, and flavone glycosides or flavonol glycosides as copigment are made to coexist in the cells of flower organ such as petals.

Abstract: A variable resistance non-volatile memory device includes a memory cell array including memory cells, a write circuit, and a control circuit. Each memory cell includes a memory element that is a non-volatile and variable-resistance memory element, and a cell transistor. The write circuit includes a source line driver circuit connected to the cell transistor and a bit line driver circuit connected to the memory element. When performing a write operation of changing the memory element to a low resistance state, the control circuit performs control for allowing current having a first current value to flow through the memory element, and subsequently performs control for allowing current having a second current value to flow through the memory element. The second current value is greater than the largest value of overshoot current flowing through the memory element after the start of the changing of the memory element to the low resistance state.

Abstract: [Problem] To provide: a film which is for aging meat and which is relatively easy to treat and allows meat to be aged more safely and effectively; and a film which is for preserving meat and can effectively suppress the deterioration of color or the like of fresh meat. [Solution] The present invention relates to a film for preserving meat, the film being characterized by: (1) including a hydrogen generating layer containing hydrogen generating particles which can generate a molecular hydrogen upon reacting with water; and (2) using the film in a state in which the hydrogen generating layer is directly contacted with the surface of the meat.

Abstract: A variable resistance non-volatile memory device includes a memory cell array including memory cells, a write circuit, and a control circuit. Each memory cell includes a memory element that is a non-volatile and variable-resistance memory element, and a cell transistor. The write circuit includes a source line driver circuit connected to the cell transistor and a bit line driver circuit connected to the memory element. When performing a write operation of changing the memory element to a low resistance state, the control circuit performs control for allowing current having a first current value to flow through the memory element, and subsequently performs control for allowing current having a second current value to flow through the memory element. The second current value is greater than the largest value of overshoot current flowing through the memory element after the start of the changing of the memory element to the low resistance state.

Abstract: The purpose of the present invention is to provide a breeding method for a plant having a blue flower color with a simpler blue color development controlling technique, without requiring complex mechanisms for blue color development that have been previously presented and techniques reproducing such mechanisms. Delphinidin-based anthocyanins, in which the both 3? and 5?-positions of the anthocyanin B-ring have been glycosylated, and flavone glycosides or flavonol glycosides as copigment are made to coexist in the cells of flower organ such as petals.

Abstract: Connection weight coefficients to be used in a neural network computation are stored in a memory array. A word line drive circuit drives a word line corresponding to input data of a neural network. A column selection circuit connects to a computation circuit bit lines to which a connection weight coefficient to be computed is connected. The computation circuit determines the sum of cell currents flowing in the bit lines. A result of the determination made by the computation circuit is stored in an output holding circuit, and is set as an input of a neural network in the next layer, to the word line drive circuit. A control circuit instructs the word line drive circuit and the column selection circuit to select the word line and the bit line to be used in the neural network computation, based on information held in a network configuration information holding circuit.

Abstract: A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a memory element and a transistor are connected in series between data lines, a memory element and a transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data. A current application circuit has a function of adjusting current values flowing in data lines, and adjusts connection weight coefficients without rewriting the memory elements.

Abstract: A neural network computation circuit that outputs output data according to a result of a multiply-accumulate operation between input data and connection weight coefficients, the neural network computation circuit includes computation units in each of which a non-volatile semiconductor memory element and a cell transistor are connected in series between data lines, a non-volatile semiconductor memory element and a cell transistor are connected in series between data lines, and gates of the transistors are connected to word lines. The connection weight coefficients are stored into the non-volatile semiconductor memory elements. A word line selection circuit places the word lines in a selection state or a non-selection state according to the input data. A determination circuit determines current values flowing in data lines to output output data.

Abstract: A neural network computation circuit includes in-area multiple-word line selection circuits that are provided in one-to-one correspondence to a plurality of word line areas into which a plurality of word lines included in a memory array are logically divided. Each of the in-area multiple-word line selection circuits sets one or more word lines in a selected state or a non-selected state, and includes a first latch and a second latch provided for each word line.

Abstract: An image forming apparatus includes a latent image bearer to bear a latent image, a potential sensor having a vibrator driven by a drive frequency to detect a surface potential of the latent image bearer, a developer bearer to bear developer that develops the latent image on the latent image bearer, and a power supply to apply a superimposed voltage obtained by superimposing an alternating voltage on a direct current voltage on the developer bearer. The frequency of the alternating voltage is not a multiple of the drive frequency and is a value obtained by adding a predetermined value to a multiple of the driving frequency.

Abstract: An electrophotographic image forming apparatus includes a latent image bearer to rotate and bear a latent image, a charging device to charge the a latent image bearer, a developing device to develop the latent image with developer including toner and use a developing voltage including an AC component, and a lubricant applicator to apply lubricant onto a surface of the latent image bearer. An amount of the lubricant applied by the lubricant applicator onto the latent image bearer per centimeter in an axial direction of the latent image bearer is equal to or greater than 0.845 mg for a running distance of 1.0 kilometer of the latent image bearer, and a difference between a largest value and a smallest value of the developing voltage is in a range of 200 V to 400 V.

Abstract: An image forming apparatus includes a latent image bearer to bear a latent image, a potential sensor having a vibrator driven by a drive frequency to detect a surface potential of the latent image bearer, a developer bearer to bear developer that develops the latent image on the latent image bearer, and a power supply to apply a superimposed voltage obtained by superimposing an alternating voltage on a direct current voltage on the developer bearer. The frequency of the alternating voltage is not a multiple of the drive frequency and is a value obtained by adding a predetermined value to a multiple of the driving frequency.

Abstract: A nonvolatile semiconductor storage apparatus is provided. To a data node and a reference node, a first transistor and a second transistor are respectively connected. In a data state determining operation, in the case where voltage is applied to the data node and reference node, the first and second transistors operate as precharge transistors in a first operation mode, and operate as mirror transistors in a second operation mode. The first and second operation modes are switched.

Abstract: An electrophotographic image forming apparatus includes a latent image bearer to rotate and bear a latent image, a charging device to charge the a latent image bearer, a developing device to develop the latent image with developer including toner and use a developing voltage including an AC component, and a lubricant applicator to apply lubricant onto a surface of the latent image bearer. An amount of the lubricant applied by the lubricant applicator onto the latent image bearer per centimeter in an axial direction of the latent image bearer is equal to or greater than 0.845 mg for a running distance of 1.0 kilometer of the latent image bearer, and a difference between a largest value and a smallest value of the developing voltage is in a range of 200 V to 400 V.

Abstract: A memory array includes a plurality of memory cells arranged in a matrix, each memory cell including a cell transistor and a variable resistance element connected to an end of the cell transistor, and a cell transistor performance measuring cell including a MOS transistor. The cell transistor performance measuring cell is used to stabilize resistance values in a low resistance state and a high resistance state of the variable resistance element irrespective of variations in the cell transistor and thereby improve read characteristics and reliability characteristics of a nonvolatile semiconductor storage device.

Abstract: An image forming apparatus includes an image bearer, a transfer member, and a power source. The image bearer includes a plurality of layers. The transfer member forms a transfer nip between the image bearer and the transfer member. The power source outputs a transfer bias to transfer a toner image from the image bearer onto a recording sheet in the transfer nip. The transfer bias alternates between a transfer-side bias that causes the toner image to move from the image bearer to the recording sheet, and an opposite-side bias different from the transfer-side bias. A duty ratio of a time period, during which the opposite-side bias is output, relative to one cycle of a waveform, is greater than 50%.