Patents by Inventor Masayoshi Yagyu
Masayoshi Yagyu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11229115Abstract: In a multilayer wiring board having through holes used in an electronic device, wiring is efficiently performed at high density while preventing crosstalk of differential signals. A wiring board includes: a plurality of pads arranged linearly at a predetermined pitch; a plurality of through holes arranged in parallel along an arrangement direction of the pads; and a wiring pattern connecting the pad to the through hole. Between the through holes connected to the pads which are connected to the ground via the wiring patterns, two through holes through which each of a pair of differential signals constituting a differential signal pair passes are provided such that a direction of a straight line connecting the two through holes is inclined to the arrangement direction of the pads.Type: GrantFiled: December 13, 2017Date of Patent: January 18, 2022Assignee: Hitachi, Ltd.Inventors: Norio Chujo, Yutaka Uematsu, Masayoshi Yagyu
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Patent number: 10763214Abstract: Performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip and a chip component that are electrically connected to each other via a wiring substrate. The semiconductor chip includes an input/output circuit and an electrode pad electrically connected to the input/output circuit and transmitting the signal. The chip component includes a plurality of types of passive elements and includes an equalizer circuit for correcting signal waveforms of the signal, and electrodes electrically connected to the equalizer circuit. The path length from the signal electrode of the semiconductor chip to the electrode of the chip component is 1/16 or more and 3.5/16 or less with respect to the wavelength of the signal.Type: GrantFiled: May 7, 2019Date of Patent: September 1, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Shuuichi Kariyazaki, Kazuyuki Nakagawa, Keita Tsuchiya, Yosuke Katsura, Shinji Katayama, Norio Chujo, Masayoshi Yagyu, Yutaka Uematsu
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Publication number: 20200260570Abstract: In a multilayer wiring board having through holes used in an electronic device, wiring is efficiently performed at high density while preventing crosstalk of differential signals. A wiring board includes: a plurality of pads arranged linearly at a predetermined pitch; a plurality of through holes arranged in parallel along an arrangement direction of the pads; and a wiring pattern connecting the pad to the through hole. Between the through holes connected to the pads which are connected to the ground via the wiring patterns, two through holes through which each of a pair of differential signals constituting a differential signal pair passes are provided such that a direction of a straight line connecting the two through holes is inclined to the arrangement direction of the pads.Type: ApplicationFiled: December 13, 2017Publication date: August 13, 2020Inventors: Norio CHUJO, Yutaka UEMATSU, Masayoshi YAGYU
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Patent number: 10541216Abstract: A semiconductor device includes a semiconductor chip mounted over a wiring substrate. A signal wiring for input for transmitting input signals to the semiconductor chip and a signal wiring for output for transmitting output signals from the semiconductor chip are placed in different wiring layers in the wiring substrate and overlap with each other. In the direction of thickness of the wiring substrate, each of the signal wirings is sandwiched between conductor planes supplied with reference potential. In the front surface of the semiconductor chip, a signal electrode for input and a signal electrode for output are disposed in different rows. In cases where the signal wiring for output is located in a layer higher than the signal wiring for input in the wiring substrate, the signal electrode for output is placed in a row closer to the outer edge of the front surface than the signal electrode for input.Type: GrantFiled: October 30, 2018Date of Patent: January 21, 2020Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Kazuyuki Nakagawa, Keita Tsuchiya, Yoshiaki Sato, Shuuichi Kariyazaki, Norio Chujo, Masayoshi Yagyu, Yutaka Uematsu
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Publication number: 20190363050Abstract: Performance of a semiconductor device is improved. The semiconductor device includes a semiconductor chip and a chip component that are electrically connected to each other via a wiring substrate. The semiconductor chip includes an input/output circuit and an electrode pad electrically connected to the input/output circuit and transmitting the signal. The chip component includes a plurality of types of passive elements and includes an equalizer circuit for correcting signal waveforms of the signal, and electrodes electrically connected to the equalizer circuit. The path length from the signal electrode of the semiconductor chip to the electrode of the chip component is 1/16 or more and 3.5/16 or less with respect to the wavelength of the signal.Type: ApplicationFiled: May 7, 2019Publication date: November 28, 2019Inventors: Shuuichi KARIYAZAKI, Kazuyuki NAKAGAWA, Keita TSUCHIYA, Yosuke KATSURA, Shinji KATAYAMA, Norio CHUJO, Masayoshi YAGYU, Yutaka UEMATSU
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Publication number: 20190198462Abstract: A semiconductor device includes a semiconductor chip mounted over a wiring substrate. A signal wiring for input for transmitting input signals to the semiconductor chip and a signal wiring for output for transmitting output signals from the semiconductor chip are placed in different wiring layers in the wiring substrate and overlap with each other. In the direction of thickness of the wiring substrate, each of the signal wirings is sandwiched between conductor planes supplied with reference potential. In the front surface of the semiconductor chip, a signal electrode for input and a signal electrode for output are disposed in different rows. In cases where the signal wiring for output is located in a layer higher than the signal wiring for input in the wiring substrate, the signal electrode for output is placed in a row closer to the outer edge of the front surface than the signal electrode for input.Type: ApplicationFiled: October 30, 2018Publication date: June 27, 2019Inventors: Kazuyuki NAKAGAWA, Keita TSUCHIYA, Yoshiaki SATO, Shuuichi KARIYAZAKI, Norio CHUJO, Masayoshi YAGYU, Yutaka UEMATSU
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Patent number: 8358708Abstract: A low offset input circuit and a signal transmission system which can accommodate a high-speed interface and achieve reduction of an offset voltage are provided. An offset voltage compensating circuit block 103 having an input circuit block 108 including an input circuit 104 and an adder-subtractor circuit block 105, switches 108, 109, a detecting circuit block 106, and an adjusting and holding circuit block 107 is provided. To compensate for an offset voltage of the input circuit block 102, an offset voltage of the input circuit block 102 is detected at the detecting circuit block 106 by turning on the switches 108, 109, and the detected offset voltage is held in the adjusting and holding circuit block 107, and negative feedback of the held offset voltage to the adder-subtractor circuit block 105 is performed. Thereby, signals Vop, Von having compensated offset voltages are outputted from the input circuit block 102.Type: GrantFiled: May 28, 2009Date of Patent: January 22, 2013Assignee: Hitachi, Ltd.Inventors: Takashi Takemoto, Hiroki Yamashita, Masayoshi Yagyu
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Publication number: 20120302075Abstract: The present invention maintains plugging-unplugging durability of connector pins for connecting to a signal wiring board, as well as reduces a stub length of a through hole connecting to a signal wiring. In the signal wiring board according to the present invention, a through hole connecting to the inner-layer signal wiring is formed to be shorter than the other through holes. A through hole in which a connector pin connecting to the inner-layer signal wiring is inserted is formed to have a length corresponding to a depth of the inner-layer signal wiring.Type: ApplicationFiled: May 25, 2012Publication date: November 29, 2012Applicant: Hitachi, Ltd.Inventors: Satoshi MURAOKA, Masayoshi YAGYU
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Patent number: 8284872Abstract: A burst mode receiver including a CDR circuit that does not perform bit synchronization determination at a wrong position even when a burst signal waveform containing a distortion is input is provided. The burst mode receiver includes a CDR circuit for reproducing clock and data from a received signal, a bit synchronization determination circuit for determining whether the CDR circuit is in an optimum phase, a waveform distortion determination circuit for determining from the received signal whether there is waveform distortion, and a CDR output enable determination circuit for determining whether an output of the CDR circuit is valid or invalid. The CDR output enable determination circuit performs CDR output enable determination based on a bit synchronization determination result and a waveform distortion determination result.Type: GrantFiled: January 14, 2010Date of Patent: October 9, 2012Assignee: Hitachi, Ltd.Inventors: Jun Sugawa, Hiroki Ikeda, Masayoshi Yagyu
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Patent number: 7965765Abstract: In an adjustment method of waveform equalization coefficient, one of jitter and amplitude is measured only in a case of an arbitrary signal sequence and a waveform equalization coefficient is adjusted. Particularly, using a signal of received signals other than a 010 signal or a 101 signal, code inversion time is measured. Since the code inversion time in a case where such signals are used becomes steeper in comparison with that in the conventional technique, adjustment time of the waveform equalization coefficient can be reduced.Type: GrantFiled: December 28, 2007Date of Patent: June 21, 2011Assignee: Hitachi, Ltd.Inventors: Hisaaki Kanai, Norio Chujo, Masayoshi Yagyu
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Patent number: 7795944Abstract: In a signal transmission system where an influence of the circuit characteristic variation of an input circuit on signal receiving operation cannot be ignored, there is provided a method of realizing a low-offset input circuit which is capable of conducting high-speed operation and always continuing signal receiving operation without increasing the number of terminals of a semiconductor integrated circuit and without the necessity of providing additional signal observing means and variation adjustment amount calculating means to the external of the semiconductor integrated circuit.Type: GrantFiled: July 31, 2008Date of Patent: September 14, 2010Assignee: Hitachi, Ltd.Inventors: Masayoshi Yagyu, Hiroki Yamashita, Takashi Takemoto
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Patent number: 7768330Abstract: For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an “H” level and a latch part that latches a data output signal from the data acquisition part when the click signal is an “L” level. The gain control part is provided between common nodes of NMOS transistors in the differential amplifier and serves to make the gain of the differential amplifier higher in a high frequency band than in a low frequency band. When the clock signal is an “L” level, the common node control part serves to control an electrical charge so as to eliminate a potential difference between the common nodes. Thus, the transition time of the data output signal is speeded up and the setup margin is increased in the latch part. The above described technique can therefore speed up operations of various logic circuits such as a latch circuit.Type: GrantFiled: December 26, 2007Date of Patent: August 3, 2010Assignee: Hitachi, Ltd.Inventors: Fumio Yuuki, Hiroki Yamashita, Masayoshi Yagyu, Koji Fukuda
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Publication number: 20100183107Abstract: A burst mode receiver including a CDR circuit that does not perform bit synchronization determination at a wrong position even when a burst signal waveform containing a distortion is input is provided. The burst mode receiver includes a CDR circuit for reproducing clock and data from a received signal, a bit synchronization determination circuit for determining whether the CDR circuit is in an optimum phase, a waveform distortion determination circuit for determining from the received signal whether there is waveform distortion, and a CDR output enable determination circuit for determining whether an output of the CDR circuit is valid or invalid. The CDR output enable determination circuit performs CDR output enable determination based on a bit synchronization determination result and a waveform distortion determination result.Type: ApplicationFiled: January 14, 2010Publication date: July 22, 2010Applicant: HITACHI, LTD.Inventors: Jun SUGAWA, Hiroki IKEDA, Masayoshi YAGYU
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Publication number: 20090304092Abstract: A low offset input circuit and a signal transmission system which can accommodate a high-speed interface and achieve reduction of an offset voltage are provided. An offset voltage compensating circuit block 103 having an input circuit block 108 including an input circuit 104 and an adder-subtractor circuit block 105, switches 108, 109, a detecting circuit block 106, and an adjusting and holding circuit block 107 is provided. To compensate for an offset voltage of the input circuit block 102, an offset voltage of the input circuit block 102 is detected at the detecting circuit block 106 by turning on the switches 108, 109, and the detected offset voltage is held in the adjusting and holding circuit block 107, and negative feedback of the held offset voltage to the adder-subtractor circuit block 105 is performed. Thereby, signals Vop, Von having compensated offset voltages are outputted from the input circuit block 102.Type: ApplicationFiled: May 28, 2009Publication date: December 10, 2009Inventors: Takashi TAKEMOTO, Hiroki YAMASHITA, Masayoshi YAGYU
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Publication number: 20090085632Abstract: In a signal transmission system where an influence of the circuit characteristic variation of an input circuit on signal receiving operation cannot be ignored, there is provided a method of realizing a low-offset input circuit which is capable of conducting high-speed operation and always continuing signal receiving operation without increasing the number of terminals of a semiconductor integrated circuit and without the necessity of providing additional signal observing means and variation adjustment amount calculating means to the external of the semiconductor integrated circuit.Type: ApplicationFiled: July 31, 2008Publication date: April 2, 2009Inventors: Masayoshi YAGYU, Hiroki YAMASHITA, Takashi TAKEMOTO
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Publication number: 20080204100Abstract: For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an “H” level and a latch part that latches a data output signal from the data acquisition part when the click signal is an “L” level. The gain control part is provided between common nodes of NMOS transistors in the differential amplifier and serves to make the gain of the differential amplifier higher in a high frequency band than in a low frequency band. When the clock signal is an “L” level, the common node control part serves to control an electrical charge so as to eliminate a potential difference between the common nodes. Thus, the transition time of the data output signal is speeded up and the setup margin is increased in the latch part. The above described technique can therefore speed up operations of various logic circuits such as a latch circuit.Type: ApplicationFiled: December 26, 2007Publication date: August 28, 2008Inventors: Fumio Yuuki, Hiroki Yamashita, Masayoshi Yagyu, Koji Fukuda
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Patent number: 7417818Abstract: A magnetic recording device capable of reducing the size of a writing circuit and the power consumption by readily adjusting the overshoot of the write current pulses is provided. Two or more transmission lines having different characteristic impedances are provided between an output driver having an impedance Zs and a magnetic head, the transmission lines are formed so that the characteristic impedances Z1, Zn?1, and Zn (n?2) thereof on the output driver side are higher than those on the magnetic recording head side (Z1>Zn?1>Zn), and the impedance Zs of the output driver is equal to or higher than the characteristic impedance Z1 of the transmission line.Type: GrantFiled: January 31, 2006Date of Patent: August 26, 2008Assignee: Hitachi, Ltd.Inventors: Fumio Yuuki, Hiroki Yamashita, Masayoshi Yagyu, Tatsuya Kawashimo
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Publication number: 20080159460Abstract: In an adjustment method of waveform equalization coefficient, one of jitter and amplitude is measured only in a case of an arbitrary signal sequence and a waveform equalization coefficient is adjusted. Particularly, using a signal of received signals other than a 010 signal or a 101 signal, code inversion time is measured. Since the code inversion time in a case where such signals are used becomes steeper in comparison with that in the conventional technique, adjustment time of the waveform equalization coefficient can be reduced.Type: ApplicationFiled: December 28, 2007Publication date: July 3, 2008Inventors: Hisaaki Kanai, Norio Chujo, Masayoshi Yagyu
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Patent number: 7373114Abstract: This invention provides a signal transmission circuit, a signal output circuit, and a termination method of a signal transmission circuit capable of preventing the re-reflection of the signal at a transmitting node of a transmission path even when an impedance of a signal output circuit does not match a characteristic impedance of a transmission path. On a signal transmission circuit composed of a transmission path, a signal output circuit connected to a transmitting node of the transmission path, and a signal receiver circuit connected to a receiving node of the signal transmission path, in order to prevent the re-reflection of an output signal of a signal output unit at the transmitting node via the receiving node, a correction current generator unit is provided for outputting correction current with a predetermined current amount and at a predetermined timing set in a current amount/timing control section, to the transmitting node.Type: GrantFiled: January 7, 2005Date of Patent: May 13, 2008Assignee: Hitachi, Ltd.Inventors: Masayoshi Yagyu, Hiroki Yamashita, Fumio Yuuki, Tatsuya Kawashimo
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Patent number: 7319575Abstract: This invention provides a semiconductor device in which an ESD protection circuit and a termination circuit can be realized with a small die area. A PMOS transistor having an ESD protection function is placed between a signal node on a line from an signal terminal to an input buffer and a supply voltage node. Furthermore, a voltage generator circuit is placed to supply a reference voltage to the gate of the PMOS transistor. By the reference voltage controlled by the voltage generator circuit, a source drain resistance of the PMOS transistor is set. Thereby, the PMOS transistor can be made to function as a terminating resistor whose resistance can be set adaptively to a characteristic impedance of a transmission line, for example, connected to the signal terminal in addition to the ESD protection function.Type: GrantFiled: November 29, 2005Date of Patent: January 15, 2008Assignee: Hitachi, Ltd.Inventors: Tatsuya Kawashimo, Hiroki Yamashita, Masayoshi Yagyu