Abstract: Provided is a multilayer container including a polyester layer containing a polyester resin (X), and a polyamide layer containing a polyamide resin (Y), a yellowing inhibitor (A), and an oxidation accelerator (B). The content of the polyamide resin (Y) is from 0.05 to 7.0 mass % relative to the total amount of all polyamide layers and all polyester layers. The yellowing inhibitor (A) is a dye, and the content of the yellowing inhibitor (A) is from 1 to 30 ppm relative to the total amount of all polyamide layers and all polyester layers.

Abstract: A semiconductor device includes an operation resource which performs a plurality of ECU functions, a peripheral resource which is shared by the plurality of ECU functions and a control mechanism which controls a period in which one of the ECU functions uses the peripheral resource. The control mechanism calculates, based on a budget value which is given in advance and is a performance allocation, a use prohibition period in which the one of the ECU functions is prohibited from using the peripheral resource within the predetermined unit time.

Abstract: Provided is a single-layer container containing a polyester resin (X), a polyamide resin (Y), a blue colorant (A), and a red colorant (B). The content of the polyamide resin (Y) is from 0.05 to 7.0 mass%, and the content of the blue colorant (A) is from 1 to 40 ppm.

Abstract: Provided is a multilayer container having a polyester layer containing a polyester resin (X), and a polyamide layer containing a polyamide resin (Y) and a yellowing inhibitor (A). The content of the polyamide resin (Y) is from 0.05 to 7.0 mass % relative to the total amount of all polyamide layers and all polyester layers. The yellowing inhibitor (A) is a dye. The content of the yellowing inhibitor (A) is from 400 to 800 ppm relative to the polyamide layer. An L* of the multilayer container is 87.5 or greater.

Abstract: Provided is a multilayer container including: a polyester layer containing a polyester resin (X); and a polyamide layer containing a polyamide resin (Y) and a yellowing inhibitor (A). The content of the polyamide resin (Y) is from 0.05 to 7.0 mass % relative to a total amount of all polyamide layers and all polyester layers, and the content of the yellowing inhibitor (A) is from 1 to 30 ppm relative to the total amount of all polyamide layers and all polyester layers. Also provided are a method for manufacturing the multilayer container, and a method for manufacturing a recycled polyester, the method thereof including a step of recovering polyester from the multilayer container.

Abstract: Provided is a multilayer container including: a polyester layer containing a polyester resin (X); and a polyamide layer containing a polyamide resin (Y) and a yellowing inhibitor (A). The content of the polyamide resin (Y) is from 0.05 to 7.0 mass % relative to a total amount of all polyamide layers and all polyester layers, and the content of the yellowing inhibitor (A) is from 1 to 30 ppm relative to the total amount of all polyamide layers and all polyester layers. Also provided are a method for manufacturing the multilayer container, and a method for manufacturing a recycled polyester, the method thereof including a step of recovering polyester from the multilayer container.

Abstract: Provided is a multilayer container including a polyester layer containing a polyester resin (X), and a polyamide layer containing a polyamide resin (Y), a yellowing inhibitor (A), and an oxidation accelerator (B). The content of the polyamide resin (Y) is from 0.05 to 7.0 mass% relative to the total amount of all polyamide layers and all polyester layers. The yellowing inhibitor (A) is a dye, and the content of the yellowing inhibitor (A) is from 1 to 30 ppm relative to the total amount of all polyamide layers and all polyester layers.

Abstract: Provided is a multilayer container including: a polyester layer containing a polyester resin (X); and a polyamide layer containing a polyamide resin (Y) and a yellowing inhibitor (A). The content of the polyamide resin (Y) is from 0.05 to 7.0 mass % relative to a total amount of all polyamide layers and all polyester layers, and the content of the yellowing inhibitor (A) is from 1 to 30 ppm relative to the total amount of all polyamide layers and all polyester layers. Also provided are a method for manufacturing the multilayer container, and a method for manufacturing a recycled polyester, the method thereof including a step of recovering polyester from the multilayer container.

Abstract: A semiconductor device includes an operation resource which performs a plurality of ECU functions, a peripheral resource which is shared by the plurality of ECU functions and a control mechanism which controls a period in which one of the ECU functions uses the peripheral resource. The control mechanism calculates, based on a budget value which is given in advance and is a performance allocation, a use prohibition period in which the one of the ECU functions is prohibited from using the peripheral resource within the predetermined unit time.

Abstract: A semiconductor device includes an operation resource which performs a plurality of ECU functions, a peripheral resource which is shared by the plurality of ECU functions and a control mechanism which controls a period in which one of the ECU functions uses the peripheral resource. The control mechanism calculates, based on a budget value which is given in advance and is a performance allocation, a use prohibition period in which the one of the ECU functions is prohibited from using the peripheral resource within the predetermined unit time.

Abstract: A semiconductor device includes an operation resource which performs a plurality of ECU functions, a peripheral resource which is shared by the plurality of ECU functions and a control mechanism which controls a period in which one of the ECU functions uses the peripheral resource. The control mechanism calculates, based on a budget value which is given in advance and is a performance allocation, a use prohibition period in which the one of the ECU functions is prohibited from using the peripheral resource within the predetermined unit time.

Abstract: The present invention provides a polyimide resin composition capable of forming a film having heat resistance and transparency and, in addition thereto, mechanical strength, surface hardness and flex resistance, a polyimide resin, a polyimide film and a laminate. The present invention includes: a polyimide resin composition containing a polyimide resin that has structural units represented by specific structures in a specific ratio, containing silica fine particles; the polyimide resin; a polyimide film; and a laminate.

Abstract: A multiprocessor system including a first processor element, and a second processor element that includes a CPU, a shared resource unit shared by the first and second processor elements, a protection setting unit and a guard unit, and the protection setting unit sets an access protection range for the shared resource unit, the guard unit restricts an access request from the first processor element to the shared resource unit based on the access protection range, the guard unit issues an exceptional access notification signal when the access request from the first processor element is within the access protection range, and when the exceptional access notification signal is issued, the CPU extends the access protection range in such a manner that the extended access protection range is wider than the access protection range set before issue of the exceptional access notification signal.

Abstract: In a conventional multiprocessor system, an access right with respect to a shared resource could not be changed in a flexible manner. The present invention provides a multiprocessor system having a first processor element (PE-A) and a second processor element (PE-B), the first processor element (PE-A) and the second processor element (PE-B) independently executing a program, in which the first processor element (PE-A) includes: a central processing unit (CPUa) for performing an operation processing based upon the program; a shared resource (18a) which is shared between the first processor element (PE-A) and the second processor element (PE-B); and a guard unit (16a) for restricting an access request from the second processor element (PE-B) to the shared resource (18a) based upon an access protection range setting value designated by the central processing unit (CPUa).

Abstract: A filter operation circuit of a microprocessor executes an IIR filter operation by using data provided from registers R0 to R2 and outputs one sample of data Y[n] subjected to filter operation and transfer data P[n] to be used in the next IIR filter operation. Register R0 provides filter coefficients to the filter operation circuit. Register R1 provides past transfer data P[n?1] and P[n?2] to the filter operation circuit and is overwritten and updated with new transfer data P[n] output from the filter operation circuit. Register R2 holds multiple samples of data X[n] to X[n+3] to be subjected to filter operation and provides X[n] to the filter operation circuit. An area of register R2 in which X[n] has been held is overwritten and updated with Y[n].

Abstract: Provided is a microcomputer having the improved flexibility in changing correspondences between exception causes and exception vectors. The microcomputer includes: a vector candidate output section capable of outputting a plurality of vector candidates; an address selecting section selecting, as an exception vector, one of the vector candidates according to an exception cause; an instruction execution section starting an exception processing routine by accessing a memory area specified by the exception vector; and a correspondence changing section changing the number of exception causes associated with at least one of address candidates included in the vector candidates.

Abstract: A filter operation circuit of a microprocessor executes an IIR filter operation by using data provided from registers R0 to R2 and outputs one sample of data Y[n] subjected to filter operation and transfer data P[n] to be used in the next IIR filter operation. Register R0 provides filter coefficients to the filter operation circuit. Register R1 provides past transfer data P[n?1] and P[n?2] to the filter operation circuit and is overwritten and updated with new transfer data P[n] output from the filter operation circuit. Register R2 holds multiple samples of data X[n] to X[n+3] to be subjected to filter operation and provides X[n] to the filter operation circuit. An area of register R2 in which X[n] has been held is overwritten and updated with Y[n].

Abstract: Provided is a microcomputer having the improved flexibility in changing correspondences between exception causes and exception vectors. The microcomputer includes: a vector candidate output section capable of outputting a plurality of vector candidates; an address selecting section selecting, as an exception vector, one of the vector candidates according to an exception cause; an instruction execution section starting an exception processing routine by accessing a memory area specified by the exception vector; and a correspondence changing section changing the number of exception causes associated with at least one of address candidates included in the vector candidates.

Abstract: In a conventional multiprocessor system, an access right with respect to a shared resource could not be changed in a flexible manner. The present invention provides a multiprocessor system having a first processor element (PE-A) and a second processor element (PE-B), the first processor element (PE-A) and the second processor element (PE-B) independently executing a program, in which the first processor element (PE-A) includes: a central processing unit (CPUa) for performing an operation processing based upon the program; a shared resource (18a) which is shared between the first processor element (PE-A) and the second processor element (PE-B); and a guard unit (16a) for restricting an access request from the second processor element (PE-B) to the shared resource (18a) based upon an access protection range setting value designated by the central processing unit (CPUa).

Abstract: An access of a processor having an access right to a shared resource is affected by the polling operation of a processor having no access right. A multiprocessor system having a plurality of processors, and a shared resource that can be accessed by the plural processors, the multiprocessor system includes a shared bus that connects the plural processors to the shared resource, a mutual exclusion control unit that holds identification information indicating which processor has an access right to the shared resource among the plural processors, and a local bus that connects the mutual exclusion control unit and the plural processors.