Patents by Inventor Masayuki Dohi

Masayuki Dohi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230021003
    Abstract: An information processing apparatus includes an acquiring unit, a determining unit, and a notifying unit. The acquiring unit acquires a facial image of a first visitor that has visited a predetermined place to be visited, and attribute information indicating an attribute of the first visitor at a time of visit. The determining unit determines when a second visitor visits the predetermined place to be visited, whether a same person as the second visitor is included among the first visitors by verification between a facial image of the first and second visitor. The notifying unit notifies, when attribute information corresponding to the first visitor that has been determined as the same person as the second visitor indicates a specific attribute, that a subject person, an attribute of which is the specific attribute at least at the time of visit has visited again as the second visitor.
    Type: Application
    Filed: November 17, 2021
    Publication date: January 19, 2023
    Applicant: JAPAN COMPUTER VISION CORP.
    Inventors: Nozomu HAYASHIDA, Kanako DOHI, Masayuki MOTOSHIMA, Tatsuaki BANDO
  • Publication number: 20220083284
    Abstract: A USB memory according to a present embodiment is the USB memory capable of data transfer by being connected with a receptacle, and includes a wiring board, a semiconductor chip, a connector, and an adhesive film. The wiring board includes wiring. The semiconductor chip is electrically connected with the wiring. The connector includes a first connection, a second connection, and a holder. The first connection is electrically connected with the semiconductor chip via the wiring. The second connection is electrically connected with the first connection and is connectable with the receptacle. The holder holds the first connection and the second connection. The adhesive film is provided at least between the wiring board and the holder.
    Type: Application
    Filed: March 15, 2021
    Publication date: March 17, 2022
    Applicant: Kioxia Corporation
    Inventor: Masayuki DOHI
  • Patent number: 10503685
    Abstract: According to one embodiment, a semiconductor memory device includes a first tube, a case, a substrate, a memory, a controller, and a first layer. The case is connected to the first tube. The substrate includes a first portion inside the first tube. The first layer covers an inner face of the first tube, is interposed between the first portion and the first tube, and has a thermal conductivity higher than a thermal conductivity of the first tube.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: December 10, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Masayuki Dohi
  • Patent number: 10290983
    Abstract: According to one embodiment, an electronic device includes a substrate, a male connector, and conductive members. The substrate includes conductors on a surface of the substrate. The male connector is mounted on the substrate and insertable into a female connector complying with a USB Type-C standard. The conductive members are mounted in the male connector, each of the conductive members electrically connecting one of twenty-four terminals complying with the USB Type-C standard mounted in the female connector with one of the conductors when the male connector is inserted into the female connector, and a number of the conductive members being less than twenty-four.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: May 14, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shiro Harashima, Masayuki Dohi
  • Publication number: 20180309249
    Abstract: According to one embodiment, an electronic device includes a substrate, a male connector, and conductive members. The substrate includes conductors on a surface of the substrate. The male connector is mounted on the substrate and insertable into a female connector complying with a USB Type-C standard. The conductive members are mounted in the male connector, each of the conductive members electrically connecting one of twenty-four terminals complying with the USB Type-C standard mounted in the female connector with one of the conductors when the male connector is inserted into the female connector, and a number of the conductive members being less than twenty-four.
    Type: Application
    Filed: June 28, 2018
    Publication date: October 25, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Shiro Harashima, Masayuki Dohi
  • Patent number: 10038285
    Abstract: According to one embodiment, an electronic device includes a substrate, a male connector, and conductive members. The substrate includes conductors on a surface of the substrate. The male connector is mounted on the substrate and insertable into a female connector complying with a USB Type-C standard. The conductive members are mounted in the male connector, each of the conductive members electrically connecting one of twenty-four terminals complying with the USB Type-C standard mounted in the female connector with one of the conductors when the male connector is inserted into the female connector, and a number of the conductive members being less than twenty-four.
    Type: Grant
    Filed: September 8, 2016
    Date of Patent: July 31, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Shiro Harashima, Masayuki Dohi
  • Publication number: 20170257960
    Abstract: According to one embodiment, a semiconductor memory device includes a first tube, a case, a substrate, a memory, a controller, and a first layer. The case is connected to the first tube. The substrate includes a first portion inside the first tube. The first layer covers an inner face of the first tube, is interposed between the first portion and the first tube, and has a thermal conductivity higher than a thermal conductivity of the first tube.
    Type: Application
    Filed: August 31, 2016
    Publication date: September 7, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Masayuki DOHI
  • Publication number: 20170250507
    Abstract: According to one embodiment, an electronic device includes a substrate, a male connector, and conductive members. The substrate includes conductors on a surface of the substrate. The male connector is mounted on the substrate and insertable into a female connector complying with a USB Type-C standard. The conductive members are mounted in the male connector, each of the conductive members electrically connecting one of twenty-four terminals complying with the USB Type-C standard mounted in the female connector with one of the conductors when the male connector is inserted into the female connector, and a number of the conductive members being less than twenty-four.
    Type: Application
    Filed: September 8, 2016
    Publication date: August 31, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shiro HARASHIMA, Masayuki DOHI
  • Publication number: 20160073489
    Abstract: A module includes a base substrate, a flexible substrate including a first portion that is disposed on the substrate and a second portion that is bent from an end of the first portion toward the first portion, and a terminal exposed at the second portion of the flexible substrate. Another module includes a substrate, a convex portion disposed on the substrate, a terminal disposed on the substrate, and a first conductive member including a first portion which is disposed on the substrate and the terminal and is connected to the terminal, and a second portion extending from the first portion and along the surface of the convex portion.
    Type: Application
    Filed: March 3, 2015
    Publication date: March 10, 2016
    Inventors: Shiro HARASHIMA, Masayuki DOHI, Masaki HIGA, Takeshi MITSUHASHI, Masaaki TAKAHASHI
  • Patent number: 8778778
    Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.
    Type: Grant
    Filed: August 18, 2011
    Date of Patent: July 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazumasa Tanida, Masahiro Sekiguchi, Masayuki Dohi, Tsuyoshi Matsumura, Hideo Numata, Mari Otsuka, Naoko Yamaguchi, Takashi Shirono, Satoshi Hongo
  • Patent number: 8338918
    Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.
    Type: Grant
    Filed: June 20, 2011
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Sekiguchi, Eiji Takano, Tatsuhiko Shirakawa, Kenichiro Hagiwara, Masayuki Dohi, Susumu Harada
  • Patent number: 8339615
    Abstract: An edge detection method includes preparing a transparent substrate which includes a first main face having a first main region and a first peripheral region and a second main face having a second main region and a second peripheral region, the first peripheral region having an inclination angle of ?a1 and the second peripheral region having an inclination angle of ?a2, causing measuring light to enter the first peripheral region from a direction perpendicular to the first main region, detecting a non-emitting region where the measuring light is not emitted from the second peripheral region, and detecting an edge of the transparent substrate on the basis of the non-emitting region, wherein if a refractive index of the transparent substrate is n, the inclination angles ?a1 and ?a2satisfy the following expression: n×sin(?a1+?a2?arcsin(sin ?a1/n))?1.
    Type: Grant
    Filed: July 28, 2009
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Dohi, Itsuko Sakai, Takayuki Sakai, Shunji Kikuchi, Takuto Inoue, Akihiro Hori, Masayuki Narita
  • Publication number: 20120049312
    Abstract: According to an embodiment, an active layer is formed on a first surface of a semiconductor substrate, a wiring layer is formed on the active layer, and an insulating layer is formed covering the wiring layer. The first surface of the semiconductor substrate is bonded to a support substrate via the insulating layer, and the semiconductor substrate bonded to the support substrate is thinned leaving the semiconductor substrate having a predetermined thickness which covers the active layer from a second surface. At least a part of area of the thinned semiconductor substrate is removed to expose the active layer.
    Type: Application
    Filed: August 18, 2011
    Publication date: March 1, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazumasa TANIDA, Masahiro Sekiguchi, Masayuki Dohi, Tsuyoshi Matsumura, Hideo Numata, Mari Otsuka, Naoko Yamaguchi, Takashi Shirono, Satoshi Hongo
  • Publication number: 20110241180
    Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.
    Type: Application
    Filed: June 20, 2011
    Publication date: October 6, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahiro Sekiguchi, Eiji Takano, Tatsuhiko Shirakawa, Kenichiro Hagiwara, Masayuki Dohi, Susumu Harada
  • Patent number: 7993974
    Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.
    Type: Grant
    Filed: September 24, 2008
    Date of Patent: August 9, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Sekiguchi, Eiji Takano, Tatsuhiko Shirakawa, Kenichiro Hagiwara, Masayuki Dohi, Susumu Harada
  • Patent number: 7888760
    Abstract: A solid state imaging device includes: an imaging device substrate with an imaging device section formed on a first major surface side thereof; a backside interconnect electrode provided on a second major surface side of the imaging device substrate and electrically connected to the imaging device section, the second major surface being on the opposite side of the first major surface; a circuit substrate provided with a circuit substrate electrode opposed to the second major surface; a connecting portion electrically connecting the backside interconnect electrode to the circuit substrate electrode; and a light shielding layer provided coplanar with the backside interconnect electrode or on the circuit substrate side of the backside interconnect electrode.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: February 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hitoshi Sugiyama, Atsuko Yamashita, Kazutaka Akiyama, Susumu Harada, Masahiro Sekiguchi, Masayuki Dohi, Kazumasa Tanida, Chiaki Takubo, Hiroshi Yoshikawa, Akihiro Hori
  • Patent number: 7849897
    Abstract: An apparatus for manufacturing a semiconductor device, includes: a collet; an alignment stage; and a sheet feeding mechanism. The collet is configured to suck a surface of a semiconductor chip. The surface is on opposite side of a bonding surface to be bonded to a bonding target. The bonding surface is provided with a film-like adhesive layer. The collet includes a heater for heating the adhesive layer. The alignment stage is configured to support the semiconductor chip and to correct position of the semiconductor chip. The sheet feeding mechanism is configured to feed a release sheet onto the alignment stage.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: December 14, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shoko Omizo, Atsushi Yoshimura, Mitsuhiro Nakao, Junya Sagara, Masayuki Dohi, Tatsuhiko Shirakawa
  • Publication number: 20100027032
    Abstract: An edge detection method includes preparing a transparent substrate which includes a first main face having a first main region and a first peripheral region and a second main face having a second main region and a second peripheral region, the first peripheral region having an inclination angle of ?a1 and the second peripheral region having an inclination angle of ?a2, causing measuring light to enter the first peripheral region from a direction perpendicular to the first main region, detecting a non-emitting region where the measuring light is not emitted from the second peripheral region, and detecting an edge of the transparent substrate on the basis of the non-emitting region, wherein if a refractive index of the transparent substrate is n, the inclination angles ?a1 and ?a2 satisfy the following expression: n×sin(?a1+?a2?arcsin(sin ?a1/n))?1
    Type: Application
    Filed: July 28, 2009
    Publication date: February 4, 2010
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masayuki Dohi, Itsuko Sakai, Takayuki Sakai, Shunji Kikuchi, Takuto Inoue, Akihiro Hori, Masayuki Narita
  • Publication number: 20090194865
    Abstract: A method for manufacturing a semiconductor device, includes: preparing a semiconductor substrate with a first notch; preparing a supporting substrate with a second notch; laminating the semiconductor substrate with the supporting substrate so that the first notch can be matched with the second notch; and processing a second main surface of the semiconductor substrate opposite to a first main surface thereof facing to the supporting substrate to reduce a thickness of the semiconductor substrate to a predetermined thickness.
    Type: Application
    Filed: September 24, 2008
    Publication date: August 6, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Masahiro Sekiguchi, Eiji Takano, Tatsuhiko Shirakawa, Kenichiro Hagiwara, Masayuki Dohi, Susumu Harada
  • Publication number: 20090096051
    Abstract: A solid state imaging device includes: an imaging device substrate with an imaging device section formed on a first major surface side thereof; a backside interconnect electrode provided on a second major surface side of the imaging device substrate and electrically connected to the imaging device section, the second major surface being on the opposite side of the first major surface; a circuit substrate provided with a circuit substrate electrode opposed to the second major surface; a connecting portion electrically connecting the backside interconnect electrode to the circuit substrate electrode; and a light shielding layer provided coplanar with the backside interconnect electrode or on the circuit substrate side of the backside interconnect electrode.
    Type: Application
    Filed: October 10, 2008
    Publication date: April 16, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hitoshi SUGIYAMA, Atsuko Yamashita, Kazutaka Akiyama, Susumu Harada, Masahiro Sekiguchi, Masayuki Dohi, Kazumasa Tanida, Chiaki Takubo, Hiroshi Yoshikawa, Akihiro Hori