Patents by Inventor Masayuki Iwami

Masayuki Iwami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9960572
    Abstract: A semiconductor device includes a semiconductor layer formed of a III-V group semiconductor crystal containing As as a primary component of a V group. A V group element other than As has been introduced at a concentration of 0.02 to 5% into a V group site of the III-V group semiconductor crystal in the semiconductor layer.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: May 1, 2018
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Masayuki Iwami, Hirotatsu Ishii, Norihiro Iwai, Takeyoshi Matsuda, Akihiko Kasukawa, Takuya Ishikawa, Yasumasa Kawakita, Eisaku Kaji
  • Patent number: 9911842
    Abstract: A nitride semiconductor device includes; a semiconductor stack configured with a plurality of semiconductor layers made of nitride semiconductors provided on a base having a conductive portion; a first electrode provided on a portion of a semiconductor layer of the semiconductor layers configuring the semiconductor stack; a second electrode provided on a portion of a semiconductor layer of the semiconductor layers configuring the semiconductor stack separately from the first electrode; a first wiring provided at an upper layer of the first electrode; and a second wiring provided at an upper layer of the second electrode. A low permittivity area being a portion of which permittivity is lower than permittivities of the nitride semiconductors configuring the semiconductor stack at a lower layer of a portion of at least one of the first electrode and the second electrode other than a portion being junctioned with the semiconductor stack electrically.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: March 6, 2018
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Kazuyuki Umeno, Shinya Otomo, Keishi Takaki, Jiang Li, Takuya Kokawa, Ryosuke Tamura, Masayuki Iwami, Shusuke Kaya, Hirotatsu Ishii
  • Publication number: 20160352075
    Abstract: A semiconductor laser device includes an active layer including a well layer and a barrier layer formed of a III-V group semiconductor crystal containing As as a primary component of a V group. A V group element other than As has been introduced at a concentration of 0.02 to 5% into a V group site of the III-V group semiconductor crystal in at least one of the well layer and the barrier layer, and a III group site of the III-V group semiconductor crystal in at least one of the well layer and the barrier layer contains Al.
    Type: Application
    Filed: August 12, 2016
    Publication date: December 1, 2016
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Masayuki IWAMI, Hirotatsu ISHII, Norihiro IWAI, Takeyoshi MATSUDA, Akihiko KASUKAWA, Takuya ISHIKAWA, Yasumasa KAWAKITA, Eisaku KAJI
  • Publication number: 20160351392
    Abstract: A semiconductor device includes a semiconductor layer formed of a III-V group semiconductor crystal containing As as a primary component of a V group. A V group element other than As has been introduced at a concentration of 0.02 to 5% into a V group site of the III-V group semiconductor crystal in the semiconductor layer.
    Type: Application
    Filed: August 12, 2016
    Publication date: December 1, 2016
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Masayuki IWAMI, Hirotatsu ISHII, Norihiro IWAI, Takeyoshi MATSUDA, Akihiko KASUKAWA, Takuya ISHIKAWA, Yasumasa KAWAKITA, Eisaku KAJI
  • Publication number: 20160225889
    Abstract: A nitride semiconductor device includes; a semiconductor stack configured with a plurality of semiconductor layers made of nitride semiconductors provided on a base having a conductive portion; a first electrode provided on a portion of a semiconductor layer of the semiconductor layers configuring the semiconductor stack; a second electrode provided on a portion of a semiconductor layer of the semiconductor layers configuring the semiconductor stack separately from the first electrode; a first wiring provided at an upper layer of the first electrode; and a second wiring provided at an upper layer of the second electrode. A low permittivity area being a portion of which permittivity is lower than permittivities of the nitride semiconductors configuring the semiconductor stack at a lower layer of a portion of at least one of the first electrode and the second electrode other than a portion being junctioned with the semiconductor stack electrically.
    Type: Application
    Filed: April 13, 2016
    Publication date: August 4, 2016
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Kazuyuki UMENO, Shinya Otomo, Keishi Takaki, Jiang Li, Takuya Kokawa, Ryosuke Tamura, Masayuki Iwami, Shusuke Kaya, Hirotatsu Ishii
  • Patent number: 9269577
    Abstract: Forming a group III nitride semiconductor layer having p-type conductivity on at least one layer or more formed on an Si substrate or sapphire substrate using at least one of an epitaxial growth or ion implantation method. When forming the group III nitride semiconductor layer, at least one type of metal element selected from Zn, Li, Au, Ag, Cu, Pt, and Pd having a formation energy of a group III element substitute higher than that of Mg is doped simultaneously with Mg of a p-type dopant to introduce an interstitial site. Subsequent to activation of Mg as an acceptor, the metal element is removed from the group III nitride semiconductor layer, and the concentration of the metal element is not more than 1/100 of the concentration of Mg to realize a hole concentration of not less than 1018 to 1019 cm?3.
    Type: Grant
    Filed: October 24, 2013
    Date of Patent: February 23, 2016
    Assignee: FURUKAWA ELECTRIC CO., LTD.
    Inventor: Masayuki Iwami
  • Patent number: 9099383
    Abstract: A GaN-based semiconductor is epitaxially grown on a silicon substrate with a surface orientation of (111). The difference between the lattice constant of the GaN and the silicon (111) surface is approximately 17%, which is quite large. Therefore, the dislocation density of the grown GaN exceeds 1010 cm?2. Screw dislocation density causes the leak current of the transistor using GaN to increases. Furthermore, the mobility of the transistor is reduced. Provided is a semiconductor substrate comprising a silicon substrate and a nitride semiconductor layer that is epitaxially grown on a (150) surface of the silicon substrate.
    Type: Grant
    Filed: July 28, 2013
    Date of Patent: August 4, 2015
    Assignees: FURUKAWA ELECTRIC CO., LTD., FUJI ELECTRIC CO., LTD.
    Inventors: Masayuki Iwami, Takuya Kokawa
  • Patent number: 9048302
    Abstract: A field effect transistor has an MOS structure and is formed of a nitride based compound semiconductor. The field effect transistor includes a substrate; a semiconductor operating layer having a recess and formed on the substrate; an insulating layer formed on the semiconductor operating layer including the recess; a gate electrode formed on the insulating layer at the recess; and a source electrode and a drain electrode formed on the semiconductor operating layer with the recess in between and electrically connected to the semiconductor operating layer. The recess includes a side wall inclined relative to the semiconductor operating layer.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: June 2, 2015
    Assignee: THE FURUKAWA ELECTRIC CO., LTD
    Inventors: Yoshihiro Sato, Hiroshi Kambayashi, Yuki Niiyama, Takehiko Nomura, Seikoh Yoshida, Masayuki Iwami, Jiang Li
  • Patent number: 8884393
    Abstract: A nitride compound semiconductor device includes: a substrate; a buffer layer formed on the substrate and including a plurality of composite layers each layered of: a first layer formed of a nitride compound semiconductor; and a second layer formed of a nitride compound semiconductor containing aluminum and having a lattice constant smaller than a lattice constant of the first layer; a semiconductor operating layer formed on the buffer layer; and a plurality of electrodes formed on the semiconductor operating layer. At least one of the second layers has oxygen added therein.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: November 11, 2014
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Takuya Kokawa, Tatsuyuki Shinagawa, Masayuki Iwami, Kazuyuki Umeno, Sadahiro Kato
  • Patent number: 8860038
    Abstract: Provided is a nitride semiconductor device comprising a base substrate; a buffer layer formed above the base substrate; an active layer formed on the buffer layer; and at least two electrodes formed above the active layer. The buffer layer includes one or more composite layers that each have a plurality of nitride semiconductor layers with different lattice constants, and at least one of the one or more composite layers is doped with carbon atoms and oxygen atoms in at least a portion of a carrier region of the nitride semiconductor having the largest lattice constant among the plurality of nitride semiconductor layers, the carrier region being a region in which carriers are generated due to the difference in lattice constants between this nitride semiconductor layer and the nitride semiconductor layer formed directly thereon.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: October 14, 2014
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Masayuki Iwami, Takuya Kokawa
  • Publication number: 20140120703
    Abstract: Forming a group III nitride semiconductor layer having p-type conductivity on at least one layer or more formed on an Si substrate or sapphire substrate using at least one of an epitaxial growth or ion implantation method. When forming the group III nitride semiconductor layer, at least one type of metal element selected from Zn, Li, Au, Ag, Cu, Pt, and Pd having a formation energy of a group III element substitute higher than that of Mg is doped simultaneously with Mg of a p-type dopant to introduce an interstitial site. Subsequent to activation of Mg as an acceptor, the metal element is removed from the group III nitride semiconductor layer, and the concentration of the metal element is not more than 1/100 of the concentration of Mg to realize a hole concentration of not less than 1018 to 1019 cm?3.
    Type: Application
    Filed: October 24, 2013
    Publication date: May 1, 2014
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventor: Masayuki IWAMI
  • Publication number: 20140084298
    Abstract: A nitride compound semiconductor device includes: a substrate; a buffer layer formed on the substrate and including a plurality of composite layers each layered of: a first layer formed of a nitride compound semiconductor; and a second layer formed of a nitride compound semiconductor containing aluminum and having a lattice constant smaller than a lattice constant of the first layer; a semiconductor operating layer formed on the buffer layer; and a plurality of electrodes formed on the semiconductor operating layer. At least one of the second layers has oxygen added therein.
    Type: Application
    Filed: July 10, 2013
    Publication date: March 27, 2014
    Inventors: Takuya KOKAWA, Tatsuyuki Shinagawa, Masayuki Iwami, Kazuyuki Umeno, Sadahiro Kato
  • Publication number: 20140008661
    Abstract: A nitride-based compound semiconductor device includes a substrate, a first nitride-based compound semiconductor layer that is formed above the substrate with a buffer layer interposed between them, a second nitride-based compound semiconductor layer that is formed on the first nitride-based compound semiconductor layer and that has a larger band gap than a band gap of the first nitride-based compound semiconductor layer, and an electrode that is formed on the second nitride-based compound semiconductor layer. The second nitride-based compound semiconductor layer has a region in which carbon is doped near a surface of the second nitride-based compound semiconductor layer.
    Type: Application
    Filed: July 5, 2013
    Publication date: January 9, 2014
    Inventors: Masayuki IWAMI, Takuya KOKAWA
  • Publication number: 20140008615
    Abstract: A semiconductor device includes a substrate, a channel layer that is formed above the substrate, where the channel layer is made of a first nitride series compound semiconductor, a barrier layer that is formed on the channel layer, a first electrode that is formed on the barrier layer, and a second electrode that is formed above the channel layer. Here, the barrier layer includes a block layers and a quantum level layer. The block layer is formed on the channel layer and made of a second nitride series compound semiconductor having a larger band gap energy than the first nitride series compound semiconductor, and the quantum level layer is made of a third nitride series compound semiconductor having a smaller band gap energy than the second nitride series compound semiconductor, and has a quantum level formed therein.
    Type: Application
    Filed: July 28, 2013
    Publication date: January 9, 2014
    Applicant: ADVANCED POWER DEVICE RESEARCH ASSOCIATION
    Inventors: Makoto UTSUMI, Sadahiro KATOU, Masayuki IWAMI, Takuya KOKAWA
  • Publication number: 20130328106
    Abstract: Provided are a nitride-based semiconductor element with reduced leak current, and a manufacturing method thereof. The semiconductor element comprises a substrate; a buffer region that is formed above the substrate; an active layer that is formed on the buffer region; and at least two electrodes that are formed on the active layer. The buffer region includes a plurality of semiconductor layers having different lattice constants, and there is a substantially constant electrostatic capacitance between a bottom surface of the substrate and a top surface of the buffer region when a potential that is less than a potential of the bottom surface of the substrate is applied to the top surface of the buffer region and a voltage between the bottom surface of the substrate and the top surface of the buffer region is changed within a range corresponding to thickness of the buffer region.
    Type: Application
    Filed: August 13, 2013
    Publication date: December 12, 2013
    Applicant: Advanced Power Device Research Association
    Inventors: Takuya KOKAWA, Sadahiro KATOU, Masayuki IWAMI, Makato UTSUMI, Kazuyuki UMENO
  • Publication number: 20130307024
    Abstract: Provided is a semiconductor device that includes a substrate, a first buffer region formed over the substrate, a second buffer region formed on the first buffer region, an active layer formed on the second buffer region, and at least two electrodes formed on the active layer. The first buffer region includes at least one composite layer in which a first semiconductor layer and a second semiconductor layer are sequentially stacked. The second buffer region in includes at least one composite layer in which a third semiconductor layer, a fourth semiconductor layer, and a fifth semiconductor layer are sequentially stacked. The fourth lattice constant has a value between the third lattice constant and the fifth lattice constant.
    Type: Application
    Filed: July 28, 2013
    Publication date: November 21, 2013
    Applicant: ADVANCED POWER DEVICE RESEARCH ASSOCIATION
    Inventors: Takuya KOKAWA, Sadahiro KATOU, Masayuki IWAMI, Makoto UTSUMI
  • Publication number: 20130306979
    Abstract: A GaN-based semiconductor is epitaxially grown on a silicon substrate with a surface orientation of (111). The difference between the lattice constant of the GaN and the silicon (111) surface is approximately 17%, which is quite large. Therefore, the dislocation density of the grown GaN exceeds 1010 cm?2. Screw dislocation density causes the leak current of the transistor using GaN to increases. Furthermore, the mobility of the transistor is reduced. Provided is a semiconductor substrate comprising a silicon substrate and a nitride semiconductor layer that is epitaxially grown on a (150) surface of the silicon substrate.
    Type: Application
    Filed: July 28, 2013
    Publication date: November 21, 2013
    Applicant: ADVANCED POWER DEVICE RESEARCH ASSOCIATION
    Inventors: Masayuki IWAMI, Takuya KOKAWA
  • Publication number: 20130307023
    Abstract: Provided is a semiconductor device that has a buffer layer with which a dislocation density is decreased. The semiconductor device includes a substrate, a buffer region formed over the substrate, an active layer formed on the buffer region, and at least two electrodes formed on the active layer. The buffer region includes at least one composite layer in which a first semiconductor layer having a first lattice constant, a second semiconductor layer having a second lattice constant that is different from the first lattice constant and formed in contact with the first semiconductor layer, and a third semiconductor layer having a third lattice constant that is between the first lattice constant and the second lattice constant are sequentially laminated.
    Type: Application
    Filed: July 28, 2013
    Publication date: November 21, 2013
    Applicant: ADVANCED POWER DEVICE RESEARCH ASSOCIATION
    Inventors: Takuya KOKAWA, Sadahiro KATOU, Masayuki IWAMI, Makoto UTSUMI
  • Patent number: 8569800
    Abstract: A field effect transistor includes: a buffer layer that is formed on a substrate; a high resistance layer or a foundation layer that is formed on the buffer layer; a carbon-containing carrier concentration controlling layer that is formed on the high resistance layer or the foundation layer; a carrier traveling layer that is formed on the carrier concentration controlling layer; a carrier supplying layer that is formed on the carrier traveling layer; a recess that is formed from the carrier supplying layer up to a predetermined depth; source/drain electrodes that are formed on the carrier supplying layer with the recess intervening therebetween; a gate insulating film that is formed on the carrier supplying layer so as to cover the recess; and a gate electrode that is formed on the gate insulating film in the recess.
    Type: Grant
    Filed: March 31, 2011
    Date of Patent: October 29, 2013
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Nariaki Ikeda, Takuya Kokawa, Masayuki Iwami, Sadahiro Kato
  • Patent number: 8552531
    Abstract: A nitride-based compound semiconductor includes an atom of at least one group-III element selected from the group consisting of Al, Ga, In, and B, a nitrogen atom, and a metal atom that forms a compound by bonding with an interstitial atom of the at least one group-III element. The metal atom is preferably iron or nickel. A doping concentration of the metal atom is preferably equal to a concentration of the interstitial atom of the at least one group-III element.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: October 8, 2013
    Assignee: Advanced Power Device Research Association
    Inventor: Masayuki Iwami