Abstract: A field effect transistor includes a high resistance layer on a substrate, a semiconductor operation layer that is formed on the high resistance layer and includes a channel layer that has the carbon concentration of not more than 1×1018 cm?3 and has the layer thickness of more than 10 nm and not more than 100 nm, a recess that is formed up to the inside of the channel layer in the semiconductor operation layer, source and drain electrodes that are formed on the semiconductor operation layer with the recess intervening therebetween, a gate insulating film that is formed on the semiconductor operation layer so as to cover the recess, and a gate electrode that is formed on the gate insulating film in the recess.

Abstract: Provided is a nitride semiconductor device comprising a base substrate; a buffer layer formed above the base substrate; an active layer formed on the buffer layer; and at least two electrodes formed above the active layer. The buffer layer includes one or more composite layers that each have a plurality of nitride semiconductor layers with different lattice constants, and at least one of the one or more composite layers is doped with carbon atoms and oxygen atoms in at least a portion of a carrier region of the nitride semiconductor having the largest lattice constant among the plurality of nitride semiconductor layers, the carrier region being a region in which carriers are generated due to the difference in lattice constants between this nitride semiconductor layer and the nitride semiconductor layer formed directly thereon.

Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on said substrate, having two or more layers of composite layers in which a first semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the substrate and a second semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and smaller coefficient of thermal expansion than the first semiconductor layer are alternately laminated; a semiconductor operating layer comprising nitride based compound semiconductor formed on said buffer layer; a dislocation reducing layer comprising nitride based compound semiconductor, formed in a location between a location directly under said buffer layer and inner area of said semiconductor operating layer, and comprising a lower layer area and an upper layer area each having an uneven boundary surface, wherein threading dislocation extending from the lower layer area t

Abstract: In a GaN-based semiconductor device, an active layer of a GaN-based semiconductor is formed on a silicon substrate. A trench is formed in the active layer and extends from a top surface of the active layer to a depth reaching the silicon substrate. A first electrode is formed on an internal wall surface of the trench and extends from the top surface of the active layer to the silicon substrate. A second electrode is formed on the active layer to define a current path between the first electrode and the second electrode via the active layer in an on-state of the device. A bottom electrode is formed on a bottom surface of the silicon substrate and defines a bonding pad for the first electrode. The first electrode is formed of metal in direct ohmic contact with both the silicon substrate and the active layer.

Abstract: A nitride-based compound semiconductor includes an atom of at least one group-III element selected from the group consisting of Al, Ga, In, and B, a nitrogen atom, and a metal atom that forms a compound by bonding with an interstitial atom of the at least one group-III element. The metal atom is preferably iron or nickel, A doping concentration of the metal atom is preferably equal to a concentration of the interstitial atom of the at least one group-III element.

Abstract: A field effect transistor formed of a semiconductor of a III group nitride compound, includes an electron running layer formed on a substrate and formed of GaN; an electron supplying layer formed on the electron running layer and formed of AlxGa1-xN (0.01?x?0.4), the electron supplying layer having a band gap energy different from that of the electron running layer and being separated with a recess region having a depth reaching the electron running layer; a source electrode and a drain electrode formed on the electron supplying layer with the recess region in between; a gate insulating film layer formed on the electron supplying layer for covering a surface of the electron running layer in the recess region; and a gate electrode formed on the gate insulating film layer in the recess region. The electron supplying layer has a layer thickness between 5.5 nm and 40 nm.

Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on the substrate, the buffer layer including not less than two layers of composite layer in which a first semiconductor layer formed of a nitride-based compound semiconductor layer having a lattice constant smaller than a lattice constant of the substrate and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate and a second semiconductor layer formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate are alternately laminated; an intermediate layer provided between the substrate and the buffer layer, the intermediate layer being formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a t

Abstract: A field effect transistor includes a high resistance layer on a substrate, a semiconductor operation layer that is formed on the high resistance layer and includes a channel layer that has the carbon concentration of not more than 1×1018 cm?3 and has the layer thickness of more than 10 nm and not more than 100 nm, a recess that is formed up to the inside of the channel layer in the semiconductor operation layer, source and drain electrodes that are formed on the semiconductor operation layer with the recess intervening therebetween, a gate insulating film that is formed on the semiconductor operation layer so as to cover the recess, and a gate electrode that is formed on the gate insulating film in the recess.

Abstract: A field effect transistor includes: a buffer layer that is formed on a substrate; a high resistance layer or a foundation layer that is formed on the buffer layer; a carbon-containing carrier concentration controlling layer that is formed on the high resistance layer or the foundation layer; a carrier traveling layer that is formed on the carrier concentration controlling layer; a carrier supplying layer that is formed on the carrier traveling layer; a recess that is formed from the carrier supplying layer up to a predetermined depth; source/drain electrodes that are formed on the carrier supplying layer with the recess intervening therebetween; a gate insulating film that is formed on the carrier supplying layer so as to cover the recess; and a gate electrode that is formed on the gate insulating film in the recess

Abstract: The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron supplying layer, and a source electrode is formed on the npn laminated structure. A drain electrode is formed in a drain region of the electron supplying layer, and an insulating film is formed in an opening region formed in the gate region. When a forward voltage greater than a threshold is applied to the gate electrode, an inversion layer is formed and the drain current flows. By changing a thickness and an impurity concentration of the p-type GaN layer, the threshold voltage can be controlled. The electrical field concentration between the gate electrode and the drain electrode is relaxed due to the drift layer, and voltage resistance improves.

Abstract: The invention provides a GaN-based compound semiconductor device that is operable with low ON-resistance and high withstanding voltage. The GaN-based field effect transistor includes a buffer layer formed on a substrate, a channel layer, a drift layer formed on the channel layer, source and drain electrodes formed on the drift layer, an insulating film formed on the inner surface of a recess form in the drift layer and on the surface of the drift layer and a gate electrode formed on the insulating film and having a field plate portion. The drift layer has a reducing surface field region composed of n-type GaN-based compound semiconductor whose sheet carrier density is more than 5×1013 cm?2 and less than 1×1014 cm?2 between the recess and the drain electrode and thickness of the insulating film formed on the reducing surface field region of the drift layer is 300 nm or more.

Abstract: A semiconductor electronic device comprises a substrate; a buffer layer that comprises composite laminations of which a first semiconductor layer, that is formed of a compound semiconductor of a nitride system, that has a lattice constant to be as smaller than that of such the substrate, and that has a coefficient of thermal expansion to be as larger than that of such the substrate, and a second semiconductor layer that is formed of a compound semiconductor of a nitride system are formed as alternately on to such the substrate; a semiconductor operation layer that is formed of a compound semiconductor of a nitride system and that is formed on to such the buffer layer; and a dislocation reduction layer, which comprises a lower layer region and an upper layer region that are formed at any location at an inner side of such the buffer layer and that comprise an interface of a concave and convex shape therebetween, at which a threading dislocation that draws from such the lower layer region toward such the upper l

Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on said substrate, having two or more layers of composite layers in which a first semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the substrate and a second semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the first semiconductor layer are alternately laminated; a semiconductor operating layer comprising nitride based compound semiconductor formed on said buffer layer; a dislocation reducing layer comprising nitride based compound semiconductor, formed in a location between a location directly under said buffer layer and inner area of said semiconductor operating layer, and comprising a lower layer area and an upper layer area each having an uneven boundary surface, wherein threading dislocation extending from the lower layer area t

Abstract: A vertical semiconductor element comprises: an electro-conductive substrate; a GaN layer, as a nitride compound semiconductor layer, which is selectively grown as a convex shape on one surface of the electro-conductive substrate through a buffer layer; a source electrode as a first electrode formed on the GaN layer; and a drain electrode as a second electrode formed on another surface of the electro-conductive substrate.

Abstract: The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron supplying layer, and a source electrode is formed on the npn laminated structure. A drain electrode is formed in a drain region of the electron supplying layer, and an insulating film is formed in an opening region formed in the gate region. When a forward voltage greater than a threshold is applied to the gate electrode, an inversion layer is formed and the drain current flows. By changing a thickness and an impurity concentration of the p-type GaN layer, the threshold voltage can be controlled. The electrical field concentration between the gate electrode and the drain electrode is relaxed due to the drift layer, and voltage resistance improves.

Abstract: A field effect transistor formed of a semiconductor of a III group nitride compound, includes an electron running layer formed on a substrate and formed of GaN; an electron supplying layer formed on the electron running layer and formed of AlxGal-xN (0.01?x?0.4), the electron supplying layer having a band gap energy different from that of the electron running layer and being separated with a recess region having a depth reaching the electron running layer; a source electrode and a drain electrode formed on the electron supplying layer with the recess region in between; a gate insulating film layer formed on the electron supplying layer for covering a surface of the electron running layer in the recess region; and a gate electrode formed on the gate insulating film layer in the recess region. The electron supplying layer has a layer thickness between 5.5 nm and 40 nm.

Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on the substrate, the buffer layer including not less than two layers of composite layer in which a first semiconductor layer formed of a nitride-based compound semiconductor layer having a lattice constant smaller than a lattice constant of the substrate and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate and a second semiconductor layer formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate are alternately laminated; an intermediate layer provided between the substrate and the buffer layer, the intermediate layer being formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a t

Abstract: A field effect transistor has an MOS structure and is formed of a nitride based compound semiconductor. The field effect transistor includes a substrate; a semiconductor operating layer having a recess part and formed on the substrate; an insulating layer formed on the semiconductor operating layer including the recess part; a gate electrode formed on the insulating layer at the recess part; and a source electrode and a drain electrode formed on the semiconductor operating layer with the recess part in between and electrically connected to the semiconductor operating layer. The recess part includes a side wall protruding and inclined relative to the semiconductor operating layer.

Abstract: A GaN-based semiconductor device includes a silicon substrate; an active layer of a GaN-based semiconductor formed on the silicon substrate; a trench formed in the active layer and extending from a top surface of the active layer to the silicon substrate; a first electrode formed on an internal wall surface of the trench so that the first electrode extends from the top surface of the active layer to the silicon substrate; a second electrode formed on the active layer so that a current flows between the first electrode and the second electrode via the active layer; and a bottom electrode formed on a bottom surface of the silicon substrate. The first electrode is formed of a metal capable of being in ohmic contact with the silicon substrate and the active layer.

Abstract: A vertical semiconductor element comprises: an electro-conductive substrate 1; a GaN layer 3, as a nitride compound semiconductor layer, which is selectively grown as convex shape on an one surface of the electro-conductive substrate 1 through a buffer layer 9; a source electrode 25 as a first electrode formed on the GaN layer 3; and a drain electrode 29 as a second electrode formed on another surface of the electro-conductive substrate 1.