Patents by Inventor Masayuki Kuwabara
Masayuki Kuwabara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230341431Abstract: Provided is a technology that enables stirring of a liquid containing fine particles without providing a dedicated stirring mechanism. An automatic analyzer according to the present disclosure includes a probe that aspirates and discharges a specimen and a reagent, and a control unit that controls an operation of the probe, in which the control unit controls the probe so that the specimen, the reagent, and fine particles are dispensed to an empty vessel to obtain a liquid mixture, and a first stirring of aspirating, discharging, and stirring the liquid mixture in the vessel before precipitation of the fine particles after the dispensing, and a second stirring of aspirating, discharging, and stirring the liquid mixture in the vessel after the precipitation of the fine particles after the first stirring are performed.Type: ApplicationFiled: February 8, 2021Publication date: October 26, 2023Inventors: Masayuki KUWABARA, Mariko MIYAZAKI, Koshin HAMASAKI, Kazuhiro NODA
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Publication number: 20230333133Abstract: The purpose of the present invention is to provide an automatic analysis device capable of ensuring accuracy in a wide range of a pipetting amount without changing the rotation/vertical speed of a sampling arm and the aspiration speed of a pump. The automatic analysis device according to the present invention, which is an automatic analysis device for analyzing a target substance included in a sample, is characterized by comprising: a detection unit that analyzes the sample; and a probe that pipettes a liquid, wherein the probe changes the number of aspiration by which the liquid is aspirated into the probe according to the pipetting amount by which the probe pipettes the liquid.Type: ApplicationFiled: August 26, 2021Publication date: October 19, 2023Inventors: Kazuhiro NODA, Koshin HAMASAKI, Masayuki KUWABARA, Eiichiro TAKADA
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Reel for component mounting apparatus and component supplying method in component mounting apparatus
Patent number: 9743568Abstract: A reel for a component mounting apparatus that pulls a carrier tape out of the reel and pitch-feeds and supplies the carrier tape by a tape feeder in a component supply part and picks up a supplied component and mounts the component in a substrate by a mounting head. The reel includes: a reel core part; and the carrier tape being wound and stored around the reel core part, wherein the carrier tape includes a distal end fixed to the reel core part, and a brittle part that is positioned in the vicinity of the distal end and is broken by action of longitudinal tension in excess of a prescribed strength on the carrier tape, and the pitch-feed separates the carrier tape from the reel core part at the brittle part.Type: GrantFiled: September 2, 2014Date of Patent: August 22, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Kazunori Kanai, Masayuki Kuwabara, Hiroto Miyazaki -
Patent number: 9572295Abstract: In an electronic component mounting method, a light-emitting element is temporarily fixed to a board by solder paste and adhesive, the adhesive is cured to fix a main body of the light-emitting element to the board, and solder is melted to bond a terminal of the light-emitting element to the board. The method includes: detecting a positional deviation of an emission portion in a top surface of the light-emitting element; detecting a position of the light-emitting element in a state in which the light-emitting element is held by an absorption nozzle; positioning the emission portion to a prescribed position on the board based on the positional deviation and the position of the light-emitting element; mounting the light-emitting element on the board at a position deviated from the prescribed position by the positional deviation; curing the adhesive; and heating the board to melt the solder.Type: GrantFiled: November 25, 2015Date of Patent: February 14, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Naoki Azuma, Masayuki Kuwabara
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Publication number: 20160081243Abstract: In an electronic component mounting method, a light-emitting element is temporarily fixed to a board by solder paste and adhesive, the adhesive is cured to fix a main body of the light-emitting element to the board, and solder is melted to bond a terminal of the light-emitting element to the board. The method includes: detecting a positional deviation of an emission portion in a top surface of the light-emitting element; detecting a position of the light-emitting element in a state in which the light-emitting element is held by an absorption nozzle; positioning the emission portion to a prescribed position on the board based on the positional deviation and the position of the light-emitting element; mounting the light-emitting element on the board at a position deviated from the prescribed position by the positional deviation; curing the adhesive; and heating the board to melt the solder.Type: ApplicationFiled: November 25, 2015Publication date: March 17, 2016Inventors: Naoki AZUMA, Masayuki KUWABARA
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Patent number: 9227387Abstract: In an electronic component mounting method, a light-emitting element is temporarily fixed to a board by solder paste and adhesive, the adhesive is cured to fix a main body of the light-emitting element to the board, and solder is melted to bond a terminal of the light-emitting element to the board. The method includes: detecting a positional deviation of an emission portion in a top surface of the light-emitting element; detecting a position of the light-emitting element in a state in which the light-emitting element is held by an absorption nozzle; positioning the emission portion to a prescribed position on the board based on the positional deviation and the position of the light-emitting element; mounting the light-emitting element on the board at a position deviated from the prescribed position by the positional deviation; curing the adhesive; and heating the board to melt the solder.Type: GrantFiled: December 18, 2014Date of Patent: January 5, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Naoki Azuma, Masayuki Kuwabara
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Publication number: 20150176779Abstract: In an electronic component mounting method, a light-emitting element is temporarily fixed to a board by solder paste and adhesive, the adhesive is cured to fix a main body of the light-emitting element to the board, and solder is melted to bond a terminal of the light-emitting element to the board. The method includes: detecting a positional deviation of an emission portion in a top surface of the light-emitting element; detecting a position of the light-emitting element in a state in which the light-emitting element is held by an absorption nozzle; positioning the emission portion to a prescribed position on the board based on the positional deviation and the position of the light-emitting element; mounting the light-emitting element on the board at a position deviated from the prescribed position by the positional deviation; curing the adhesive; and heating the board to melt the solder.Type: ApplicationFiled: December 18, 2014Publication date: June 25, 2015Inventors: Naoki AZUMA, Masayuki KUWABARA
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REEL FOR COMPONENT MOUNTING APPARATUS AND COMPONENT SUPPLYING METHOD IN COMPONENT MOUNTING APPARATUS
Publication number: 20150059171Abstract: A reel for a component mounting apparatus that pulls a carrier tape out of the reel and pitch-feeds and supplies the carrier tape by a tape feeder in a component supply part and picks up a supplied component and mounts the component in a substrate by a mounting head. The reel includes: a reel core part; and the carrier tape being wound and stored around the reel core part, wherein the carrier tape includes a distal end fixed to the reel core part, and a brittle part that is positioned in the vicinity of the distal end and is broken by action of longitudinal tension in excess of a prescribed strength on the carrier tape, and the pitch-feed separates the carrier tape from the reel core part at the brittle part.Type: ApplicationFiled: September 2, 2014Publication date: March 5, 2015Inventors: Kazunori KANAI, Masayuki KUWABARA, Hiroto MIYAZAKI -
Publication number: 20120076396Abstract: A pattern inspection method and apparatus are provided for sequentially imaging plural chips formed on a substrate to be inspected to and obtaining inspection images and reference images, calculating a position gap between the inspection images and the reference images using a recipe created in advance by using another substrate of the same kind or type as the substrate, the recipe including information for determining which pattern sections are to be selected and discarded, aligning the inspection images and the reference images using information of the position gap from the calculating step, and comparing the inspection images with the reference images aligned by the aligning step and extracting a defect candidate.Type: ApplicationFiled: December 6, 2011Publication date: March 29, 2012Inventors: Kaoru SAKAI, Shunji Maeda, Takafumi Okabe, Hiroshi Goto, Masayuki Kuwabara, Naoya Takeuchi
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Patent number: 8090187Abstract: A pattern inspection method including: sequentially imaging plural chip formed on a substrate; selecting at least one of pattern sections of each inspection image obtained by the imaging, while discarding other pattern sections, based on a recipe created in advance, the recipe including information for determining which pattern sections to be selected or discarded; calculating position gap between an inspection image of a chip obtained by the imaging and a reference image stored in a memory by using positional information of pattern images included in the inspection image and reference pattern images which are both corresponding to the at least one of pattern sections selected at the selecting; aligning the inspection image and the reference image by using information of the calculated position gap; and comparing the aligned inspection image with the reference image, and extracting a difference between the two images as a defect candidate.Type: GrantFiled: March 16, 2010Date of Patent: January 3, 2012Assignees: Hitachi, Ltd., Hitachi High-Technologies CorporationInventors: Kaoru Sakai, Shunji Maeda, Takafumi Okabe, Hiroshi Goto, Masayuki Kuwabara, Naoya Takeuchi
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Publication number: 20100172570Abstract: A pattern inspection method including: sequentially imaging plural chip formed on a substrate; selecting at least one of pattern sections of each inspection image obtained by the imaging, while discarding other pattern sections, based on a recipe created in advance, the recipe including information for determining which pattern sections to be selected or discarded; calculating position gap between an inspection image of a chip obtained by the imaging and a reference image stored in a memory by using positional information of pattern images included in the inspection image and reference pattern images which are both corresponding to the at least one of pattern sections selected at the selecting; aligning the inspection image and the reference image by using information of the calculated position gap; and comparing the aligned inspection image with the reference image, and extracting a difference between the two images as a defect candidate.Type: ApplicationFiled: March 16, 2010Publication date: July 8, 2010Inventors: Kaoru SAKAI, Shunji Maeda, Takafumi Okabe, Hiroshi Goto, Masayuki Kuwabara, Naoya Takeuchi
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Patent number: 7711178Abstract: A pattern inspection method including: sequentially imaging plural chips formed on a substrate; selecting a pattern which is suitable for calculating position gap between an inspection image of a subject chip and reference image stored in memory from an image of a firstly imaged chip among said sequentially imaged plural chips formed on the substrate; computing position gap between an inspection image of a chip obtained by the sequential imaging and reference image stored in a memory by using a positional information of a pattern image included in the inspection image and a reference pattern image included in the reference image which are both corresponding to the pattern selected at the selecting; aligning the inspection image and the reference image by using information of the calculated position gap; and comparing the aligned inspection image with the reference image and extracting a difference as a defect candidate.Type: GrantFiled: October 9, 2007Date of Patent: May 4, 2010Assignees: Hitachi, Ltd., Hitachi High-Technologies CorporationInventors: Kaoru Sakai, Shunji Maeda, Takafumi Okabe, Hiroshi Goto, Masayuki Kuwabara, Naoya Takeuchi
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Publication number: 20080031511Abstract: A pattern inspection method including: sequentially imaging plural chips formed on a substrate; selecting a pattern which is suitable for calculating position gap between an inspection image of a subject chip and reference image stored in memory from an image of a firstly imaged chip among said sequentially imaged plural chips formed on the substrate; computing position gap between an inspection image of a chip obtained by the sequential imaging and reference image stored in a memory by using a positional information of a pattern image included in the inspection image and a reference pattern image included in the reference image which are both corresponding to the pattern selected at the selecting; aligning the inspection image and the reference image by using information of the calculated position gap; and comparing the aligned inspection image with the reference image and extracting a difference as a defect candidate.Type: ApplicationFiled: October 9, 2007Publication date: February 7, 2008Inventors: Kaoru Sakai, Shunji Maeda, Takafumi Okabe, Hiroshi Goto, Masayuki Kuwabara, Naoya Takeuchi
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Patent number: 7248732Abstract: A pattern inspection method and apparatus, wherein the target area is limited to a line part, having a simplified configuration and capable of detecting a killer defect as a defect candidate and considerably reducing the number of non-killer defects to be detected as defect candidates, have been disclosed. The present invention relates to a pattern inspection method and apparatus for judging non-matching parts to be defects by making a comparison between the same patterns having a line part in which a line extending in the longitudinal or transverse direction appears repetitively at a fixed pitch, wherein an average level of gray level data is calculated for each pixel columns in the direction in which the line extends, a type of the area of each pixel columns is classified into groups, a threshold value is determined for each area according to the statistical processing result of the type and the difference data of each pixel column, and the difference data is judged based on the threshold value.Type: GrantFiled: October 22, 2003Date of Patent: July 24, 2007Assignee: Tokyo Seimitsu Co., LtdInventor: Masayuki Kuwabara
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Patent number: 6980686Abstract: A pattern inspection method and a pattern inspection apparatus, which are able to detect a killer defect as a defect candidate and also reduce considerably the number of non-killer defects detected as a defect candidate, have been disclosed, wherein a differential image of two patterns to be compared is calculated, with the polarities included, and after the absolute value of the differential image is compared with a first threshold value to detect the part as a defect candidate, the polarities of the differential image of the part of the defect candidate are inspected and the part of one of the polarities is judged as a defect candidate.Type: GrantFiled: February 4, 2002Date of Patent: December 27, 2005Assignee: Tokyo Seimitsu Co., Ltd.Inventor: Masayuki Kuwabara
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Patent number: 6973208Abstract: Disclosed are a method and apparatus for inspection by pattern comparison enabling cell-cell comparison by software processing even when the array pitch R of the cells is not a whole multiple of the pixel pitch P, wherein provision is made of an imaging device for capturing an image of patterns having a plurality of basic patterns repeating at a predetermined pitch and generating pixel data, a memory for storing the image data, and an image processor unit for successively comparing corresponding pixel data of the basic patterns based on the pixel data, the image processor unit setting a first whole number by which the length of the predetermined pitch multiplied by the first whole number becomes a whole multiple of the pixel pitch when the predetermined pitch is expressed by a resolution of at least a predetermined resolution pitch smaller than the pixel pitch and successively comparing the corresponding pixel data of basic patterns said first whole number of pattern away.Type: GrantFiled: May 18, 2001Date of Patent: December 6, 2005Assignee: Tokyo Seimitsu Co., Ltd.Inventor: Masayuki Kuwabara
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Publication number: 20040086168Abstract: A pattern inspection method and apparatus, wherein the target area is limited to a line part, having a simplified configuration and capable of detecting a killer defect as a defect candidate and considerably reducing the number of non-killer defects to be detected as defect candidates, have been disclosed. The present invention relates to a pattern inspection method and apparatus for judging non-matching parts to be defects by making a comparison between the same patterns having a line part in which a line extending in the longitudinal or transverse direction appears repetitively at a fixed pitch, wherein an average level of gray level data is calculated for each pixel columns in the direction in which the line extends, a type of the area of each pixel columns is classified into groups, a threshold value is determined for each area according to the statistical processing result of the type and the difference data of each pixel column, and the difference data is judged based on the threshold value.Type: ApplicationFiled: October 22, 2003Publication date: May 6, 2004Inventor: Masayuki Kuwabara
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Publication number: 20040047501Abstract: A plurality of chips arranged in the same scanning row of a wafer is divided into groups, which include a predetermined number of chips. The images of the chips in each group are compared with each other in the double detection. If one group includes the first, the second and the third chips; the first chip and the second chip are compared, then the first chip and the third chip are compared, and at last, the second chip and the third chip are compared while the images are captured. It is therefore possible to detect the defects in the double detection for all the chips including peripheral chips by comparing the images for the same number of comparison times as the number of chips.Type: ApplicationFiled: September 9, 2003Publication date: March 11, 2004Applicant: Tokyo Seimitsu Co., Ltd.Inventor: Masayuki Kuwabara
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Patent number: 6650769Abstract: A review station comprising a wafer chuck capable of turning by at least 270 degrees, and an X-Y stage that moves over a distance one-half the diameter of a semiconductor wafer. Each of four regions obtained by dividing the surface of the semiconductor wafer 1 into four areas are successively observed using a stationary microscope 2 by turning the wafer chuck depending upon the coordinates of defective positions of the wafer to review the defects on the whole surface of the wafer.Type: GrantFiled: August 23, 1999Date of Patent: November 18, 2003Assignee: Tokyo Seimitsu Co., Ltd.Inventor: Masayuki Kuwabara
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Patent number: 6643394Abstract: A plurality of chips arranged in the same scanning row of a wafer is divided into groups, which include a predetermined number of chips. The images of the chips in each group are compared with each other in the double detection. If one group includes the first the second and the third chips; the first chip and the second chip are compared, then the first chip and the third chip are compared, and at last, the second chip and the third chip are compared while the images are captured. It is therefore possible to detect the defects in the double detection for all the chips including peripheral chips by comparing the images for the same number of comparison times as the number of chips.Type: GrantFiled: May 20, 1999Date of Patent: November 4, 2003Assignee: Tokyo Seimitsu Co., Ltd.Inventor: Masayuki Kuwabara