Patents by Inventor Mathew J. Manusharow

Mathew J. Manusharow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220028790
    Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via. Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.
    Type: Application
    Filed: October 5, 2021
    Publication date: January 27, 2022
    Inventors: Mihir K. Roy, Mathew J. Manusharow
  • Patent number: 11227825
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: January 18, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mathew J. Manusharow, Krishna Bharath, William J. Lambert, Robert L. Sankman, Aleksandar Aleksov, Brandon M. Rawlings, Feras Eid, Javier Soto Gonzalez, Meizi Jiao, Suddhasattwa Nad, Telesphor Kamgaing
  • Patent number: 11158578
    Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: October 26, 2021
    Assignee: Intel Corporation
    Inventors: Mihir K Roy, Mathew J Manusharow
  • Publication number: 20210304952
    Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.
    Type: Application
    Filed: March 26, 2021
    Publication date: September 30, 2021
    Inventors: William J. Lambert, Mihir K. Roy, Mathew J. Manusharow, Yikang Deng
  • Patent number: 10998120
    Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: May 4, 2021
    Assignee: Intel Corporation
    Inventors: William J. Lambert, Mihir K Roy, Mathew J Manusharow, Yikang Deng
  • Patent number: 10971416
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Krishna Bharath, Mathew J. Manusharow, Adel A. Elsherbini, Mihir K. Roy, Aleksandar Aleksov, Yidnekachew S. Mekonnen, Javier Soto Gonzalez, Feras Eid, Suddhasattwa Nad, Meizi Jiao
  • Publication number: 20210043572
    Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.
    Type: Application
    Filed: October 28, 2020
    Publication date: February 11, 2021
    Inventors: Mathew J. Manusharow, Jonathan Rosenfeld
  • Patent number: 10886228
    Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a first integrated circuit die, a second integrated circuit die, an organic substrate, wherein both the first integrated circuit die and the second integrated circuit die are connected to the organic substrate, a multi-die interconnect bridge (EMIB) embedded within the organic substrate, and a termination resistor associated with a circuit in the first integrated circuit die, wherein the termination resistor is located within the multi-die interconnect bridge embedded within the organic substrate.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Mathew J. Manusharow, Jonathan Rosenfeld
  • Patent number: 10847467
    Abstract: An embedded multi-die interconnect bridge (EMIB) die is configured with power delivery to the center of the EMIB die and the power is distributed to two dice that are interconnected across the EMIB die.
    Type: Grant
    Filed: October 21, 2019
    Date of Patent: November 24, 2020
    Assignee: Intel Corporation
    Inventors: Andrew Collins, Debendra Mallik, Mathew J. Manusharow, Jianyong Xie
  • Patent number: 10784204
    Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Kemal Aygun, Richard J. Dischler, Jeff C. Morriss, Zhiguo Qian, Wilfred Gomes, Yu Amos Zhang, Ram S. Viswanath, Rajasekaran Swaminathan, Sriram Srinivasan, Yidnekachew S. Mekonnen, Sanka Ganesan, Eduard Roytman, Mathew J. Manusharow
  • Patent number: 10734282
    Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Harold Ryan Chase, Mihir K Roy, Mathew J Manusharow, Mark Hlad
  • Publication number: 20200111745
    Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.
    Type: Application
    Filed: October 14, 2019
    Publication date: April 9, 2020
    Inventors: Mihir K. Roy, Mathew J. Manusharow
  • Publication number: 20200066641
    Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.
    Type: Application
    Filed: July 2, 2016
    Publication date: February 27, 2020
    Inventors: Kemal AYGUN, Richard J. DISCHLER, Jeff C. MORRISS, Zhiguo QIAN, Wilfred GOMES, Yu Amos ZHANG, Ram S. VISWANATH, Rajasekaran SWAMINATHAN, Sriram SRINIVASAN, Yidnekachew S. MEKONNEN, Sanka GANESAN, Eduard ROYTMAN, Mathew J. MANUSHAROW
  • Publication number: 20200051916
    Abstract: An embedded multi-die interconnect bridge (EMIB) die is configured with power delivery to the center of the EMIB die and the power is distributed to two dice that are interconnected across the EMIB die.
    Type: Application
    Filed: October 21, 2019
    Publication date: February 13, 2020
    Inventors: Andrew COLLINS, Debendra MALLIK, Mathew J. MANUSHAROW, Jianyong XIE
  • Patent number: 10522455
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: December 31, 2019
    Assignee: INTEL CORPORATION
    Inventors: Mathew J. Manusharow, Dustin P. Wood, Debendra Mallik
  • Patent number: 10490503
    Abstract: An embedded multi-die interconnect bridge (EMIB) die is configured with power delivery to the center of the EMIB die and the power is distributed to two dice that are interconnected across the EMIB die.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: November 26, 2019
    Assignee: Intel Corporation
    Inventors: Andrew Collins, Debendra Mallik, Mathew J Manusharow, Jianyong Xie
  • Publication number: 20190355636
    Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.
    Type: Application
    Filed: July 30, 2019
    Publication date: November 21, 2019
    Inventors: Krishna Bharath, Mathew J. Manusharow, Adel A. Elsherbini, Mihir K. Roy, Aleksandar Aleksov, Yidnekachew S. Mekonnen, Javier Soto Gonzalez, Feras Eid, Suddhasattwa Nad, Meizi Jiao
  • Patent number: 10453795
    Abstract: A ground isolation webbing structure package includes a top level with an upper interconnect layer having upper ground contacts, upper data signal contacts, and a conductive material upper ground webbing structure that is connected to the upper ground contacts and surrounds the upper data signal contacts. The upper contacts may be formed over and connected to via contacts or traces of a lower layer of the same interconnect level. The via contacts of the lower layer may be connected to upper contacts of a second interconnect level which may also have such webbing. There may also be at least a third interconnect level having such webbing. The webbing structure electrically isolates and reduces cross talk between the signal contacts, thus providing higher frequency and more accurate data signal transfer between devices such as integrated circuit (IC) chips attached to a package.
    Type: Grant
    Filed: December 26, 2015
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Yu Amos Zhang, Mathew J. Manusharow, Kemal Aygun, Mohiuddin Mazumder
  • Patent number: 10446499
    Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Mihir K Roy, Mathew J Manusharow
  • Publication number: 20190304911
    Abstract: An embedded multi-die interconnect bridge (EMIB) die is configured with power delivery to the center of the EMIB die and the power is distributed to two dice that are interconnected across the EMIB die.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 3, 2019
    Inventors: Andrew Collins, Debendra Mallik, Mathew J. Manusharow, Jianyong Xie