Patents by Inventor Mathew J. Manusharow
Mathew J. Manusharow has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180331003Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, the electrical package may include a first package layer. A plurality of signal lines with a first thickness may be formed on the first package layer. Additionally, a power plane with a second thickness may be formed on the first package layer. According to an embodiment, the second thickness is greater than the first thickness. Embodiments of the invention may form the power plane with a lithographic patterning and deposition process that is different than the lithographic patterning and deposition process used to form the plurality of signal lines. In an embodiment, the power plane may be formed concurrently with vias that electrically couple the signal lines to the next routing layer.Type: ApplicationFiled: December 16, 2015Publication date: November 15, 2018Inventors: Krishna BHARATH, Mathew J. MANUSHAROW, Adel A. ELSHERBINI, Mihir K. ROY, Aleksandar ALEKSOV, Yidnekachew S. MEKONNEN, Javier SOTO GONZALEZ, Feras EID, Suddhasattwa NAD, Meizi JIAO
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Patent number: 10121701Abstract: Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.Type: GrantFiled: July 26, 2016Date of Patent: November 6, 2018Assignee: Intel CorporationInventors: Harold Ryan Chase, Mihir K. Roy, Mathew J. Manusharow, Mark Hlad
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Publication number: 20180315690Abstract: Embodiments of the invention include an electrical package and methods of forming the package. In one embodiment, a transformer may be formed in the electrical package. The transformer may include a first conductive loop that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first conductive loop from a second conductive loop that is formed in the package. Additional embodiments of the invention include forming a capacitor formed in the electrical package. For example, the capacitor may include a first capacitor plate that is formed over a first dielectric layer. A thin dielectric spacer material may be used to separate the first capacitor plate form a second capacitor plate that is formed in the package. The thin dielectric spacer material in the transformer and capacitor allow for increased coupling factors and capacitance density in electrical components.Type: ApplicationFiled: December 21, 2015Publication date: November 1, 2018Inventors: Adel A. ELSHERBINI, Mathew J. MANUSHAROW, Krishna BHARATH, William J. LAMBERT, Robert L. SANKMAN, Aleksandar ALEKSOV, Brandon M. RAWLINGS, Feras EID, Javier SOTO GONZALEZ, Meizi JIAO, Suddhasattwa NAD, Telesphor KAMGAING
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Patent number: 10085341Abstract: A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.Type: GrantFiled: March 16, 2017Date of Patent: September 25, 2018Assignee: Intel CorporationInventors: Mihir K. Roy, Mathew J. Manusharow
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Publication number: 20180226310Abstract: Embodiments of the invention include package substrates that include microchannels and methods of making such package substrates. In an embodiment, the package substrate may include a first package layer. In some embodiments, a bottom channel wall may be formed over the first package layer. Embodiments may also include a channel sidewall that is formed in contact with the bottom channel wall. An organic dielectric layer may be formed over the first package layer. However, embodiments include a package substrate where the dielectric layer is not present within a perimeter of the channel sidewall. Additionally, a top channel wall may be supported by the channel sidewall. According to an embodiment, the top channel wall, the channel sidewall, and the bottom channel wall define a microchannel.Type: ApplicationFiled: September 25, 2015Publication date: August 9, 2018Inventors: Feras EID, Adel A. ELSHERBINI, Henning BRAUNISCH, Yidnekachew MEKONNEN, Krishna BHARATH, Mathew J. MANUSHAROW, Aleksandar ALEKSOV, Nathan FRITZ
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Publication number: 20180213655Abstract: This disclosure relates generally to an electronic chip package that can include a die and a buildup layer substantially enveloping the die. Electrical interconnects can be electrically coupled to the die and passing, at least in part, through the buildup layer. An optical emitter can be electrically coupled to the die with a first one of the electrical interconnects and configured to emit light from a first major surface of the electronic chip package. A solder bump can be electrically coupled to the die with a second one of the electrical interconnects and positioned on a second major surface of the electronic chip package different from the first major surface.Type: ApplicationFiled: March 21, 2018Publication date: July 26, 2018Inventors: Mihir K. Roy, Mathew J. Manusharow
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Patent number: 10008451Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.Type: GrantFiled: February 28, 2017Date of Patent: June 26, 2018Assignee: Intel CorporationInventors: Chia-Pin Chiu, Zhiguo Qian, Mathew J. Manusharow
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Patent number: 9992871Abstract: Discussed generally herein are methods and devices for altering an effective series resistance (ESR) of a component. A device can include a substrate including electrical connection circuitry therein, a first via hole through a first surface of the substrate and contiguous with the electrical connection circuitry, a first conductive polymer with a resistance greater than a resistance of the electrical connection circuitry filling the first via hole, and a component electrically coupled to the first conductive polymer.Type: GrantFiled: November 10, 2015Date of Patent: June 5, 2018Assignee: Intel CorporationInventors: William J. Lambert, Mathew J Manusharow
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Patent number: 9899311Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).Type: GrantFiled: December 6, 2016Date of Patent: February 20, 2018Assignee: Intel CorporationInventors: Mathew J. Manusharow, Daniel N. Sobieski, Mihir K. Roy, William J. Lambert
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Patent number: 9741686Abstract: Some embodiments relate to an electronic package. The electronic package includes a substrate that includes a plurality of buildup layers. A first die is embedded in one of the buildup layers on one side of the substrate. A second die is bonded to the substrate within a cavity on an opposing side of the substrate. The first die and the second die may be electrically connected to conductors within the plurality of buildup layers. Other embodiments relate to method of connecting a first die to a second die to form an electronic package. The method includes attaching a first die to a core and fabricating a substrate onto the core. The method further includes creating a cavity in another of the buildup layers on an opposing side of the substrate and attaching a second die to the substrate within the cavity.Type: GrantFiled: February 29, 2016Date of Patent: August 22, 2017Assignee: Intel CorporationInventors: Harold Ryan Chase, Mathew J Manusharow, Mihir K Roy
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Publication number: 20170221828Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for a bridge interconnect assembly that can be embedded in a package assembly. In one embodiment, a package assembly includes a package substrate configured to route electrical signals between a first die and a second die and a bridge embedded in the package substrate and configured to route the electrical signals between the first die and the second die, the bridge including a bridge substrate, one or more through-hole vias (THVs) formed through the bridge substrate, and one or more traces disposed on a surface of the bridge substrate to route the electrical signals between the first die and the second die. Routing features including traces and a ground plane of the bridge interconnect assembly may be separated by an air gap. Other embodiments may be described and/or claimed.Type: ApplicationFiled: February 28, 2017Publication date: August 3, 2017Inventors: Chia-Pin Chiu, Zhiguo Qian, Mathew J. Manusharow
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Publication number: 20170188460Abstract: A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.Type: ApplicationFiled: March 16, 2017Publication date: June 29, 2017Inventors: Mihir K. Roy, Mathew J. Manusharow
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Publication number: 20170187419Abstract: Embodiments are generally directed to a shielded bundle interconnect. An embodiment of an apparatus includes multiple signal bundles, the signal bundles including a first signal bundle including a first plurality of signals and a second signal bundle including a second plurality of signals; and a lithographic via shielding to provide electromagnetic shielding, the lithographic via shielding located at least in part between the first signal bundle and the second signal bundle, wherein the lithographic via shielding includes at least a via generated by a lithographic via process. The lithographic via shielding partially or completely surrounds at least one of the signal bundles of the apparatus.Type: ApplicationFiled: December 26, 2015Publication date: June 29, 2017Inventors: Yu Zhang, Mathew J. Manusharow, Adel A. Elsherbini, Henning Braunisch, Kemal Aygun
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Publication number: 20170178786Abstract: Devices and methods including a though-hole inductor for an electronic package are shown herein. Examples of the through-hole inductor include a substrate including at least one substrate layer. Each substrate layer including a dielectric layer having a first surface and a second surface. An aperture included in the dielectric layer is located from the first surface to the second surface. The aperture includes an aperture wall from the first surface to the second surface. A conductive layer is deposited on the first surface, second surface, and the aperture wall. At least one coil is cut from the conductive layer and located on the aperture wall.Type: ApplicationFiled: December 17, 2015Publication date: June 22, 2017Inventors: William J. Lambert, Mihir K. Roy, Mathew J. Manusharow, Yikang Deng
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Publication number: 20170162509Abstract: Embodiments that allow both high density and low density interconnection between microelectronic die and motherboard via Direct Chip Attach (DCA) are described. In some embodiments, microelectronic die have a high density interconnect with a small bump pitch located along one edge and a lower density connection region with a larger bump pitch located in other regions of the die. The high density interconnect regions between die are interconnected using an interconnecting bridge made out of a material that can support high density interconnect manufactured into it, such as silicon. The lower density connection regions are used to attach interconnected die directly to a board using DCA. The high density interconnect can utilize current Controlled Collapsed Chip Connection (C4) spacing when interconnecting die with an interconnecting bridge, while allowing much larger spacing on circuit boards.Type: ApplicationFiled: February 21, 2017Publication date: June 8, 2017Inventors: Mihir K. Roy, Mathew J. Manusharow
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Publication number: 20170154842Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for designing and assembling a die capable of being adapted to a number of different packaging configurations. In one embodiment an integrated circuit (IC) die may include a semiconductor substrate. The die may also include an electrically insulative material disposed on the semiconductor substrate; a plurality of electrical routing features disposed in the electrically insulative material to route electrical signals through the electrically insulative material; and a plurality of metal features disposed in a surface of the electrically insulative material. In embodiments, the plurality of metal features may be electrically coupled with the plurality of electrical routing features. In addition, the plurality of metal features may have an input/output (I/O) density designed to enable the die to be integrated with a plurality of different package configurations. Other embodiments may be described and/or claimed.Type: ApplicationFiled: April 25, 2014Publication date: June 1, 2017Inventors: Mathew J. MANUSHAROW, Dustin P. WOOD, Debendra MALLIK
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Publication number: 20170135211Abstract: Discussed generally herein are methods and devices for altering an effective series resistance (ESR) of a component. A device can include a substrate including electrical connection circuitry therein, a first via hole through a first surface of the substrate and contiguous with the electrical connection circuitry, a first conductive polymer with a resistance greater than a resistance of the electrical connection circuitry filling the first via hole, and a component electrically coupled to the first conductive polymer.Type: ApplicationFiled: November 10, 2015Publication date: May 11, 2017Inventors: William J. Lambert, Mathew J. Manusharow
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Patent number: 9633938Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).Type: GrantFiled: September 25, 2015Date of Patent: April 25, 2017Assignee: Intel CorporationInventors: Mathew J. Manusharow, Daniel N. Sobieski, Mihir K. Roy, William J. Lambert
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Patent number: 9622350Abstract: A circuit board upon which to mount an integrated circuit chip may include a first interconnect zone on the surface of the circuit board having first contacts with a first pitch, and a second interconnect zone, surrounding the first zone, having second contacts or traces with a second pitch that is smaller than the first pitch. The first contacts may have a design rule (DR) for direct chip attachment (DCA) to an integrated circuit chip. The first contacts may be formed by bonding a sacrificial substrate having the first contacts to a surface of the board; or by laser scribing trenches where the conductor will be plated to create the first contacts. Such a board allows DCA of smaller footprint processor chips for devices, such as tablet computers, cell phones, smart phones, and value phone devices.Type: GrantFiled: September 28, 2013Date of Patent: April 11, 2017Assignee: Intel CorporationInventors: Mihir K. Roy, Mathew J. Manusharow
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Publication number: 20170092575Abstract: A hybrid pitch package includes a standard package pitch zone of the package having only standard package pitch sized features that is adjacent to a smaller processor pitch sized zone of the package having smaller processor pitch sized features. The package may be formed by obtaining a package having standard package pitch sized features (such as from another location or a package processing facility), forming a protective mask over a standard package pitch zone of the package that is adjacent to a smaller processor pitch sized zone on the package, and then forming smaller processor pitch sized features (such as contacts, traces and interconnects) in the smaller processor pitch sized zone at a chip fabrication processing facility. The smaller processor pitch sized features can be directly connected to (thus reducing the package connection area needed) a chip or device having processor pitch sized features (e.g., exposed contacts).Type: ApplicationFiled: December 6, 2016Publication date: March 30, 2017Inventors: Mathew J. Manusharow, Daniel N. Sobieski, Mihir K. Roy, William J. Lambert