Abstract: A merge sort circuit can include a parallel merge sort core that performs a partial merge on two input tuples, each containing a number P of data elements sorted according to a sort key, to produce a sorted output tuple of P data elements. Input data blocks to be merged can be stored in first and second block buffers. The block buffers can receive data from a vector memory read interface that reads groups of at least P data elements at a time. Loading of data elements into the block buffers can be based on respective fill levels of the block buffers.

Abstract: This disclosure relates to techniques for performing wireless communications including filtering packets for transmission between a user equipment (UE) and a base station. Techniques for filtering packets using higher layer information, such as a flow identifier, are disclosed. A device may generate various tables and may use the tables to filter packets efficiently.

Abstract: A merge sort circuit can include a parallel merge sort core that performs a partial merge on two input tuples, each containing a number P of data elements sorted according to a sort key, to produce a sorted output tuple of P data elements. Input data blocks to be merged can be stored in first and second block buffers. The block buffers can receive data from a vector memory read interface that reads groups of at least P data elements at a time. Loading of data elements into the block buffers can be based on respective fill levels of the block buffers.

Abstract: This disclosure relates to techniques for performing wireless communications including filtering packets for transmission between a user equipment (UE) and a base station. Techniques for filtering packets using higher layer information, such as a flow identifier, are disclosed. A device may generate various tables and may use the tables to filter packets efficiently.

Abstract: This disclosure relates to techniques for performing wireless communications including filtering packets for transmission between a user equipment (UE) and a base station. Techniques for filtering packets using higher layer information, such as a flow identifier, are disclosed. A device may generate various tables and may use the tables to filter packets efficiently.

Abstract: Certain aspects of the present disclosure relate to wireless communications, and more particularly, to techniques for preparing data for transmission from a user equipment in a wireless communication system. In some embodiments, a method may limit memory access starts during a time interval to ensure that all memory access operations are completed with a transmission time interval.

Abstract: Certain aspects of the present disclosure relate to wireless communications, and more particularly, to techniques for preparing data for transmission from a user equipment in a wireless communication system. In some embodiments, a method may limit memory access starts during a time interval to ensure that all memory access operations are completed with a transmission time interval.

Abstract: Aspects of the present disclosure provide methods and apparatus for offloading checksum processing in a user equipment (UE) (e.g., from an application processor to a modem processor). Such offloading may speed up packet processing, increase data rate, and/or free up resources of the application processor for other tasks.

Abstract: Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.

Abstract: Systems and methods for wireless communications are provided. These include data deciphering components, interrupt processing components, adaptive aggregations methods, optimized data path processing, buffer pool processing, application processing where data is formatted in a suitable format for a destination process, and Keystream bank processing among other hardware acceleration features. Such systems and methods are provided to simplify logic designs and mitigate processing steps during wireless network data processing.

Abstract: Multiple memory pools are defined in hardware for operating on data. At least one memory pool has a lower latency that the other memory pools. Hardware components operate directly on data in the lower latency memory pool.

Abstract: Incoming data frames are parsed by a hardware component. Headers are extracted and stored in a first location along with a pointer to the associated payload. Payloads are stored in a single, contiguous memory location.

Abstract: Aspects of the present disclosure provide methods and apparatus for offloading checksum processing in a user equipment (UE) (e.g., from an application processor to a modem processor). Such offloading may speed up packet processing, increase data rate, and/or free up resources of the application processor for other tasks.

Abstract: An apparatus and method for distributed data processing is described herein. A main processor programs a mini-processor to process an incoming data stream. The mini-processor is located in close proximity to hardware components operating on the input data stream. A copy engine is also provided for copying data from multiple protocol data units in a single copy operation.

Abstract: Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.

Abstract: Incoming data frames are parsed by a hardware component. Headers are extracted and stored in a first location along with a pointer to the associated payload. Payloads are stored in a single, contiguous memory location.

Abstract: Multiple memory pools are defined in hardware for operating on data. At least one memory pool has a lower latency that the other memory pools. Hardware components operate directly on data in the lower latency memory pool.

Abstract: Systems and methods for wireless communications are provided. These include data deciphering components, interrupt processing components, adaptive aggregations methods, optimized data path processing, buffer pool processing, application processing where data is formatted in a suitable format for a destination process, and Keystream bank processing among other hardware acceleration features. Such systems and methods are provided to simplify logic designs and mitigate processing steps during wireless network data processing.