Abstract: An integrated circuit including a substrate of a semiconductor material having first and second opposite surfaces and including active areas leveling the first surface. The integrated circuit includes a device of protection against laser attacks, the protection device includes at least one first doped region extending between at least part of the active areas and the second surface, a device for biasing the first region, and a device for detecting an increase in the current provided by the biasing device.

Abstract: A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstructs at least one part of the read address from the memory cells selection signals, and supplies a first reconstructed address able to detect an error injection affecting the selection signals. Particularly but not exclusively applicable to the integrated circuits for chip cards.

Abstract: The present invention relates to a non-volatile memory comprising a memory array comprising functional memory cells and non-functional memory cells linked to at least one non-functional word line. A word line address decoder comprises a special decoding section linked to the non-functional word line, for selecting the non-functional word line when a functional word line is read-selected, such that non-functional memory cells are selected simultaneously with the functional memory cells, and distort the reading of the functional memory cells. Application particularly to integrated circuits for smart cards.

Abstract: A method processes parallel electrical signals, using parallel processing circuits that process successive cycles of electrical signals according to a rule for allocating electrical signals to the processing circuits. The method comprises, between the processing cycles, a step of modifying the rule for allocating electrical signals to the processing circuits, so that a processing circuit processes electrical signals of different ranks during different processing cycles. The method can be applied particularly to secure a memory during read phases of the memory and of an integrated circuit with a microprocessor using such a memory.

Abstract: A memory comprises memory cells arranged in a memory array, and an address decoder to apply memory cells selection signals to the memory array according to a read address applied to the memory. The memory comprises an address reconstruction circuit which reconstructs at least one part of the read address from the memory cells selection signals, and supplies a first reconstructed address able to detect an error injection affecting the selection signals. Particularly but not exclusively applicable to the integrated circuits for chip cards.

Abstract: The present invention relates to a non-volatile memory comprising a memory array comprising functional memory cells and non-functional memory cells linked to at least one non-functional word line. A word line address decoder comprises a special decoding section linked to the non-functional word line, for selecting the non-functional word line when a functional word line is read-selected, such that non-functional memory cells are selected simultaneously with the functional memory cells, and distort the reading of the functional memory cells. Application particularly to integrated circuits for smart cards.

Abstract: The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.

Abstract: The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.

Abstract: The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.

Abstract: An EEPROM cell is described as having a screening metal structure formed of preference in the first metal layer and located in substantial overlaying relationship at the floating gate terminal. This defeats the possibility of anomalous readings being obtained by measuring the amount of charge on the floating gate terminal. An additional screening metal structure, to be formed in the third and following metal layers, may be provided to fully overlie the cell and provide additional protection against anomalous readings.

Abstract: The disclosure relates to detectors of the level of supply voltage in an integrated circuit. The disclosed detector is designed to detect the crossing of low levels of supply voltage. It comprises a first arm to define a first reference voltage and a second arm to define a second reference voltage, these two reference voltages varying differently as a function of the supply voltage and their curves of variation intersecting for a value of the supply voltage located close to a desired threshold. A comparator receives the two reference voltages. The first arm has a resistive divider bridge, an intermediate connector of which constitutes the first reference voltage. The second arm comprises a resistor series-connected with a native P type MOS transistor, the point of junction of this resistor and this transistor constituting the second reference voltage. A non-linear element may be parallel-connected to the resistor which constitutes the first reference voltage.

Abstract: The access to memory words of an integrated circuit is protected by the creation of a decision table that receives addresses of instruction words and/or data words to be protected and that receives also addresses of the control bits of a control word assigned to a word to be protected. It can be shown that this mode of action provides greater security through the use of a decision table made in wired circuit form as well as greater flexibility through the programmable quality of the control words assigned to each memory word to be controlled.

Abstract: To form a ramp signal for the programming of a memory cell without losing excess voltage in a control circuit, the output of a voltage pull-up circuit is connected to the programming input using a P type transistor. It is shown that this P type transistor then charges the memory array at constant current, prompting a linear increase of the voltage. This results in preventing the memory cell that is to be programmed from being subjected to excessively sudden variations of voltage. It is shown that by acting in this way, the integrated circuit can be made to work even with very low voltages.

Abstract: A voltage reference generator includes a voltage source and a differential amplifier. The voltage source supplies a stable voltage reference to a positive input of the differential amplifier which is configured as a follower having its output looped back to its negative input. The negative feedback loop is a variable-resistance loop that is controlled by the output of the differential amplifier. The variable-resistance feedback loop transiently imposes open-loop operation when the voltage reference generator is turned on so as to provide high current to the output before imposing closed-loop operation in follower mode.

Abstract: A Zener diode is used to simplify a circuit for detecting the level of an operating voltage with respect to a specified range of use. The semiconductor junction of this Zener diode is biased alternately by one voltage or another. Under these conditions, the avalanche voltage of this Zener diode changes. The operating voltage to be monitored is connected to the cathode of this Zener diode. If the monitored operating voltage is higher than the avalanche voltage of this Zener diode, the diode alternately conducts. If the operating voltage is outside this range, this diode is either permanently on or permanently off. The variations that result therefrom are detected to report whether the operating voltage is correct.

Abstract: The invention is a device to detect the logic state of a component whose impedance depends on this state, the device including means to generate a current and a measurement voltage so that the current consumption remains constant during cell detection regardless of the state detected, the device also including means to detect the logic state of the component.

Abstract: In a memory, a zone descriptor contains authorizations to act which may pertain to actions of reading, writing and erasure and which concerns memory words of a zone of the memory controlled by this descriptor. The zone descriptor also has an information element indicating the length of the memory zone by including the address of the next descriptor. An internal zone control signal is produced in order to store a mode of management of the memory zone and, an address corresponding to the end of the zone. The end of zone address is then compared with the addresses delivered by an address counter. A modification of the stored information is prompted when the end of a zone is reached.