Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

Abstract: For one disclosed embodiment, an integrated circuit may comprise an internal transmission line in one or more layers of the integrated circuit. The internal transmission line may be coupled to receive a signal from an external transmission line at a first end of the internal transmission line without use of termination circuitry. The internal transmission line may transmit the signal passively to a second end of the internal transmission line. The integrated circuit may also comprise first circuitry having an input coupled to the internal transmission line at a first location of the internal transmission line to receive the signal and second circuitry having an input coupled to the internal transmission line at a second location of the internal transmission line to receive the signal. The second location may be different from the first location. Other embodiments are also disclosed.

Abstract: A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.

Abstract: A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.

Abstract: A system and method for encoding and receiving data is provided. The data is encoded as a pulse amplitude modulated signal such that the amplitude signals do not transition from the highest signal level to the lowest signal level and do not transition from the lowest signal level to the highest signal level. The encoding and decoding is performed in some embodiments via a lookup table, and in further embodiments is designed to minimize the step between sequential pulse amplitude modulated symbols.

Abstract: A digital bus includes a transmitter unit, a receiver unit, and a transmission medium to couple the transmitter unit to the receiver unit and to provide a path for exchanging information between the transmitter unit and the receiver unit. The receiver unit includes a first-in-first-out (FIFO) unit and a synchronizer unit for receiving information from the transmitter unit. The synchronizer unit receives a plurality of write clock signals and a reset signal and generates a read reset signal positioned with respect to the plurality write clock signals and a sample clock signal. The read reset signal has a latency with respect to each of the plurality of write reset signals of between 0 and 1 clock cycles.

Abstract: A simultaneous bidirectional port coupled to a bus includes a synchronization circuit that synchronizes the port with another simultaneous data port coupled to the same bus. The synchronization circuit includes an output driver having an imbalanced output impedance, and includes a receiver with input hysteresis. The input hysteresis of the receiver is not satisfied unless both drivers with imbalanced output impedance coupled to the bus assert an output signal. Each driver asserts a signal on the bus when initialization of the corresponding simultaneous bidirectional port is complete. When both simultaneous bidirectional ports are initialized, the hysteresis of the receivers is satisfied, and each port is notified that both have been initialized.

Abstract: A device includes a bus, a first transmitter connected to the bus and configured to transmit a first signal over the bus in a first frequency band, a second transmitter connected to the bus and configured to transmit a second signal over the bus in a second frequency band at the same time that the first transmitter is transmitting the first signal, a first receiver connected to the bus and configured to receive the first signal transmitted over the bus in the first frequency band, and a second receiver connected to the bus and configured to receive the second signal transmitted over the bus in the second frequency band. The first frequency band and the second frequency band occupy different portions of the frequency spectrum.

Abstract: The invention provides, in an embodiment, an apparatus, method and means for unintrusively observing, echoing and reading signals transmitted by one of a bus and wireless communication, without disturbing electrical properties of the bus, without adding bus latency, and without adding signal discontinuities. In an aspect, a buffer having a trigger is coupled with a component that connects to a memory bus, the buffer echoes signals to an observability port, and a diagnostic device reads the echoed signals. In an aspect, the bus is one of a simultaneous bi-directional (SBD) bus having ternary logic levels, a single ended bus, a differential bus, an optically coupled bus, a chipset bus, a frontside bus, an input/output (I/O) bus, a peripheral component interface (PCI) bus, and an industry standard architecture (ISA) bus. In an aspect, the buffer echoes bus signals having frequencies between 500 MHz. and 5 GHz. In an aspect, the buffer echoes bus signals having frequencies of at least 5 GHz.

Abstract: A clock deskew method includes receiving a data signal and a clock signal, processing the data signal to generate a jitter characterization parameter, shifting the clock signal by about 90° from the jitter characterization parameter to generate a sampling clock signal, and sampling the data signal with the sampling clock signal to generate a deskewed data signal. A clock deskew unit includes a clock unit, a sampling unit, and a deskew unit. The deskew unit includes a jitter characterization unit that generates a jitter characterization parameter. The jitter characterization parameter establishes a phase location for aligning a clock signal. Shifting the clock signal by about 90° from the phase location of the jitter characterization parameter provides a location for sampling a data signal to generate a deskewed data signal.

Abstract: A digital bus includes a transmitter unit, a receiver unit, and a transmission medium to couple the transmitter unit to the receiver unit and to provide a path for exchanging information between the transmitter unit and the receiver unit. The receiver unit includes a first-in-first-out (FIFO) unit and a synchronizer unit for receiving information from the transmitter unit. The synchronizer unit receives a plurality of write clock signals and a reset signal and generates a read reset signal positioned with respect to the plurality write clock signals and a sample clock signal. The read reset signal has a latency with respect to each of the plurality of write reset signals of between 0 and 1 clock cycles.

Abstract: A digital interconnect system transmits pulses across a differential transmission line in response to transitions in an input data signal.

Abstract: In some embodiments, the invention involves a system having a first group of integrated circuits connected in a truncated ring fashion, wherein the truncated ring includes a truncated region to allow for additional integrated circuits to be added to the ring. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo ring fashion, wherein the pseudo ring is created by data flow of bi-directional signaling between the integrated circuits. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo differential arrangement in which multiple conductors carrying signals share a common reference signal conductor.

Abstract: A memory system provides includes multiple memory devices or banks of memory devices that are assigned frequency pass-bands. Each memory device includes frequency translation circuitry to up-convert and down-convert data signals to and from the assigned frequency pass-band. Some embodiments include simultaneous bidirectional communications between memory devices and a controller by assigning multiple frequency pass-bands to each memory device or bank of memory devices. A memory system substrate is provided with bandpass filters between memory device footprints and other device footprints.

Abstract: In some embodiments, the invention involves a system having a first group of integrated circuits connected in a truncated ring fashion, wherein the truncated ring includes a truncated region to allow for additional integrated circuits to be added to the ring. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo ring fashion, wherein the pseudo ring is created by data flow of bi-directional signaling between the integrated circuits. In some embodiments, the invention involves a system having a group of integrated circuits connected in a pseudo differential arrangement in which multiple conductors carrying signals share a common reference signal conductor.

Abstract: A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a clock circuit. The synchronization and clock circuit synchronizes the port with another simultaneous data port coupled to the same bus. A clock driver circuit is provided that is capable of being turned on and off. Prior to synchronization, the clock driver is off, and after synchronization, the clock driver is on. A clock receiver circuit includes a clock detection circuit to detect the presence of an input clock signal. When an integrated circuit is ready to communicate, the output clock driver is turned on and the clock detection circuit is monitored to determine when an input clock signal is received. When both the output clock driver is turned on, and an input clock signal is being received, the simultaneous bidirectional port is synchronized, and communication between integrated circuits can take place.

Abstract: A simultaneous bidirectional port coupled to a bus combines a synchronization circuit and a clock circuit. The synchronization and clock circuit synchronizes the port with another simultaneous data port coupled to the same bus. A clock driver circuit is provided that is capable of being turned on and off. Prior to synchronization, the clock driver is off, and after synchronization, the clock driver is on. A clock receiver circuit includes a clock detection circuit to detect the presence of an input clock signal. When an integrated circuit is ready to communicate, the output clock driver is turned on and the clock detection circuit is monitored to determine when an input clock signal is received. When both the output clock driver is turned on, and an input clock signal is being received, the simultaneous bidirectional port is synchronized, and communication between integrated circuits can take place.

Abstract: In some embodiments, the invention involves multiple integrated circuit stubs coupled in series. At least one of the integrated circuit stubs including first conductors to receive signals from a first adjacent one of the integrated circuit stubs, second conductors to provide signals to a second adjacent one of the integrated circuit stubs, and third conductors to provide signals to an integrated circuit chip. The integrated circuit stubs include first drivers and second drivers coupled to the first, second, and third conductors, wherein the first drivers receive the external signals from the first conductors and drive them onto the second conductors and the second drivers receive signals from the first conductors and drive them onto the third conductors.

Abstract: A synchronous clock generator for an integrated circuit is described in which a delay lock loop circuit may be used to delay a first input signal. A delay circuit is coupled to the delay lock loop circuit and receives a control voltage from the delay lock loop circuit, which is used to delay a second input signal. The first and second input signal may be complimentary.