Patents by Inventor Matthew D. Moon
Matthew D. Moon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11562519Abstract: A card creation system uses software tools on computing devices for coordinating and creating cards that include handwritten text for a recipient. The software is used to an organizer to create invitations to participate in a coordinated group card delivery for a recipient on a designated date for a specified event. The card creation invitations are distributed to invitees who can either accept or decline the invitation. The software can be used to create custom card designs that include handwritten text. The custom card designs are transmitted from the participant computing devices to a server. The card designs are reviewed, printed, and placed in separate envelopes. The printed and enveloped cards are then packaged in a single container. The single container is then sent in the card recipient on a designated delivery date.Type: GrantFiled: October 25, 2021Date of Patent: January 24, 2023Assignee: FELT, Inc.Inventors: Tomer Alpert, Gracie Everitt, Jeffrey C Schwab, Molly McIntyre, Matthew D Moon
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Patent number: 10224225Abstract: An apparatus and an associated method. The apparatus includes a chuck, an array of three or more ultrasonic sensors, a ceramic ring surrounding the chuck, and a controller connected to the ultrasonic sensors. The chuck is configured to removeably hold a substrate for processing. Each ultrasonic sensor may send a respective ultrasonic sound wave to a respective preselected peripheral region of the substrate and receive a respective return ultrasonic sound wave from the preselected peripheral region. The controller may compare a measured position of the substrate on the chuck to a specified placement of the substrate on the chuck based on a measured elapsed time between sending the ultrasonic sound wave and receiving the return ultrasonic sound wave for each ultrasonic sensor. The method compares a measured position of the substrate on the chuck to a specified position on the chuck.Type: GrantFiled: April 19, 2018Date of Patent: March 5, 2019Assignee: International Business Machines CorporationInventors: Shawn A. Adderly, Samantha D. DiStefano, Jeffrey P. Gambino, Max G. Levy, Max L. Lifson, Matthew D. Moon, Timothy D. Sullivan
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Publication number: 20180240694Abstract: An apparatus and an associated method. The apparatus includes a chuck, an array of three or more ultrasonic sensors, a ceramic ring surrounding the chuck, and a controller connected to the ultrasonic sensors. The chuck is configured to removeably hold a substrate for processing. Each ultrasonic sensor may send a respective ultrasonic sound wave to a respective preselected peripheral region of the substrate and receive a respective return ultrasonic sound wave from the preselected peripheral region. The controller may compare a measured position of the substrate on the chuck to a specified placement of the substrate on the chuck based on a measured elapsed time between sending the ultrasonic sound wave and receiving the return ultrasonic sound wave for each ultrasonic sensor. The method compares a measured position of the substrate on the chuck to a specified position on the chuck.Type: ApplicationFiled: April 19, 2018Publication date: August 23, 2018Inventors: Shawn A. Adderly, Samantha D. DiStefano, Jeffrey P. Gambino, Max G. Levy, Max L. Lifson, Matthew D. Moon, Timothy D. Sullivan
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Patent number: 9997385Abstract: An apparatus and an associated method. The apparatus includes a chuck in a process chamber, an array of three or more ultrasonic sensors in the process chamber, a ceramic ring surrounding the chuck, and a controller connected to the ultrasonic sensors. The chuck is configured to removeably hold a substrate for processing. Each ultrasonic sensor may send a respective ultrasonic sound wave to a respective preselected peripheral region of the substrate and receive a respective return ultrasonic sound wave from the preselected peripheral region. The controller may compare a measured position of the substrate on the chuck to a specified placement of the substrate on the chuck based on a measured elapsed time between sending the ultrasonic sound wave and receiving the return ultrasonic sound wave for each ultrasonic sensor. The method compares a measured position of the substrate on the chuck to a specified position on the chuck.Type: GrantFiled: April 18, 2017Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Shawn A. Adderly, Samantha D. DiStefano, Jeffrey P. Gambino, Max G. Levy, Max L. Lifson, Matthew D. Moon, Timothy D. Sullivan
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Publication number: 20170221742Abstract: An apparatus and an associated method. The apparatus includes a chuck in a process chamber, an array of three or more ultrasonic sensors in the process chary a ceramic ring surrounding the chuck, and a controller connected to the ultrasonic sensors. The chuck is configured to removeably hold a substrate for processing. Each ultrasonic sensor may send a respective ultrasonic sound wave to a respective preselected peripheral region of the substrate and receive a respective return ultrasonic sound wave from the preselected peripheral region. The controller may compare a measured position of the substrate on the chuck to a specified placement of the substrate on the chuck based on a measured elapsed time between sending the ultrasonic sound wave and receiving the return ultrasonic sound wave for each ultrasonic sensor. The method compares a measured position of the substrate on the chuck to a specified position on the chuck.Type: ApplicationFiled: April 18, 2017Publication date: August 3, 2017Inventors: Shawn A. Adderly, Samantha D. DiStefano, Jeffrey P. Gambino, Max G. Levy, Max L. Lifson, Matthew D. Moon, Timothy D. Sullivan
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Patent number: 9685362Abstract: An apparatus and method for centering substrates determining on a chuck. The apparatus includes a chuck in a process chamber, the chuck configured to removeably hold a substrate for processing; an array of two or more ultrasonic sensors arranged in the process chamber, each ultrasonic sensor arranged relative to the chuck so as to send a respective ultrasonic sound wave to a respective preselected region of the substrate and receive a respective return ultrasonic sound wave from the preselected region of the substrate; and a controller connected to each ultrasonic sensor and configured to compare a measured position of the substrate on the chuck to a specified placement of the substrate on the chuck based on a measured elapsed time between sending the ultrasonic sound wave and receiving the return ultrasonic sound wave from each ultrasonic sensor.Type: GrantFiled: February 19, 2014Date of Patent: June 20, 2017Assignee: International Business Machines CorporationInventors: Shawn A. Adderly, Samantha D. DiStefano, Jeffrey P. Gambino, Max G. Levy, Max L. Lifson, Matthew D. Moon, Timothy D. Sullivan
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Patent number: 9576863Abstract: Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are determined. Based on the backside roughness levels, the wafers are sorted into different groups. Chips having the same design are manufactured on wafers from all of the different groups. However, during manufacturing, process(es) is/are performed differently on wafers from one or more of the different groups to minimize systematic variations in a specific parameter (e.g., wire width) in the resulting chips. Specifically, because systematic variations may occur when the exact same processes are used to form IC chips on wafers with different backside roughness levels, the method disclosed herein selectively adjusts one or more of those processes when performed on wafers from one or more of the different groups to ensure that the specific parameter is approximately equal in the resulting integrated IC chips.Type: GrantFiled: December 11, 2015Date of Patent: February 21, 2017Assignee: International Business Machines CorporationInventors: Shawn A. Adderly, Kyle Babinski, Daniel A. Delibac, David A. DeMuynck, Shawn R. Goddard, Matthew D. Moon, Melissa J. Roma, Craig E. Schneider
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Patent number: 9484301Abstract: Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.Type: GrantFiled: May 21, 2015Date of Patent: November 1, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Max G. Levy, Gary L. Milo, Matthew D. Moon, Anthony C. Speranza, Timothy D. Sullivan, David C. Thomas, Steven S. Williams
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Patent number: 9390969Abstract: The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect.Type: GrantFiled: January 20, 2015Date of Patent: July 12, 2016Assignee: GlobalFoundries, Inc.Inventors: David A. DeMuynck, Zhong-Xiang He, Daniel R. Miga, Matthew D. Moon, Daniel S. Vanslette, Eric J. White
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Publication number: 20160181166Abstract: Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are determined. Based on the backside roughness levels, the wafers are sorted into different groups. Chips having the same design are manufactured on wafers from all of the different groups. However, during manufacturing, process(es) is/are performed differently on wafers from one or more of the different groups to minimize systematic variations in a specific parameter (e.g., wire width) in the resulting chips. Specifically, because systematic variations may occur when the exact same processes are used to form IC chips on wafers with different backside roughness levels, the method disclosed herein selectively adjusts one or more of those processes when performed on wafers from one or more of the different groups to ensure that the specific parameter is approximately equal in the resulting integrated IC chips.Type: ApplicationFiled: December 11, 2015Publication date: June 23, 2016Applicant: International Business Machines CorporationInventors: Shawn A. Adderly, Kyle Babinski, Daniel A. Delibac, David A. DeMuynck, Shawn R. Goddard, Matthew D. Moon, Melissa J. Roma, Craig E. Schneider
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Patent number: 9330988Abstract: Disclosed is a method of manufacturing integrated circuit (IC) chips. In the method, wafers are received and the backside roughness levels of these wafers are determined. Based on the backside roughness levels, the wafers are sorted into different groups. Chips having the same design are manufactured on wafers from all of the different groups. However, during manufacturing, process(es) is/are performed differently on wafers from one or more of the different groups to minimize systematic variations in a specific parameter (e.g., wire width) in the resulting chips. Specifically, because systematic variations may occur when the exact same processes are used to form IC chips on wafers with different backside roughness levels, the method disclosed herein selectively adjusts one or more of those processes when performed on wafers from one or more of the different groups to ensure that the specific parameter is approximately equal in the resulting integrated IC chips.Type: GrantFiled: December 23, 2014Date of Patent: May 3, 2016Assignee: International Business Machines CorporationInventors: Shawn A. Adderly, Kyle Babinski, Daniel A. Delibac, David A. DeMuynck, Shawn R. Goddard, Matthew D. Moon, Melissa J. Roma, Craig E. Schneider
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Patent number: 9275868Abstract: Substrates (wafers) with uniform backside roughness and methods of manufacture are disclosed. The method includes forming a material on a backside of a wafer. The method further includes patterning the material to expose portions of the backside of the wafer. The method further includes roughening the backside of the wafer through the patterned material to form a uniform roughness.Type: GrantFiled: July 19, 2013Date of Patent: March 1, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Shawn A. Adderly, Jeffrey P. Gambino, Max L. Lifson, Matthew D. Moon, William J. Murphy, Timothy D. Sullivan, David C. Thomas
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Publication number: 20150255395Abstract: Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.Type: ApplicationFiled: May 21, 2015Publication date: September 10, 2015Inventors: Max G. Levy, Gary L. Milo, Matthew D. Moon, Anthony C. Speranza, Timothy D. Sullivan, David C. Thomas, Steven S. Williams
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Publication number: 20150235881Abstract: An apparatus and method for centering substrates determining on a chuck. The apparatus includes a chuck in a process chamber, the chuck configured to removeably hold a substrate for processing; an array of two or more ultrasonic sensors arranged in the process chamber, each ultrasonic sensor arranged relative to the chuck so as to send a respective ultrasonic sound wave to a respective preselected region of the substrate and receive a respective return ultrasonic sound wave from the preselected region of the substrate; and a controller connected to each ultrasonic sensor and configured to compare a measured position of the substrate on the chuck to a specified placement of the substrate on the chuck based on a measured elapsed time between sending the ultrasonic sound wave and receiving the return ultrasonic sound wave from each ultrasonic sensor.Type: ApplicationFiled: February 19, 2014Publication date: August 20, 2015Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shawn A. Adderly, Samantha D. DiStefano, Jeffrey P. Gambino, Max G. Levy, Max L. Lifson, Matthew D. Moon, Timothy D. Sullivan
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Patent number: 9087839Abstract: Disclosed are semiconductor structures with metal lines and methods of manufacture which reduce or eliminate extrusion formation. The method includes forming a metal wiring comprising a layered structure of metal materials with an upper constraining layer. The method further includes forming a film on the metal wiring which prevents metal extrusion during an annealing process.Type: GrantFiled: March 29, 2013Date of Patent: July 21, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Shawn A. Adderly, Daniel A. Delibac, Zhong-Xiang He, Matthew D. Moon, Anthony C. Speranza, Timothy D. Sullivan, David C. Thomas, Eric J. White
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Patent number: 9059258Abstract: Aspects of the present invention relate to a controlled metal extrusion opening in a semiconductor structure. Various embodiments include a semiconductor structure. The structure includes an aluminum layer. The aluminum layer includes an aluminum island within the aluminum layer, and a lateral extrusion receiving opening extending through the aluminum layer adjacent the aluminum island. The opening includes a lateral extrusion of the aluminum layer of the semiconductor structure. Additional embodiments include a method of forming a semiconductor structure. The method can include forming an aluminum layer over a titanium layer. The aluminum layer includes an aluminum island within the aluminum layer. The method can also include forming an opening extending through the aluminum layer adjacent the aluminum island within the aluminum layer. The opening includes a lateral extrusion of the aluminum layer of the semiconductor layer.Type: GrantFiled: March 4, 2013Date of Patent: June 16, 2015Assignee: International Business Machines CorporationInventors: Max G. Levy, Gary L. Milo, Matthew D. Moon, Anthony C. Speranza, Timothy D. Sullivan, David C. Thomas, Steven S. Williams
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Publication number: 20150140809Abstract: The disclosure relates generally to integrated circuits (IC), IC interconnects, and methods of fabricating the same, and more particularly, high performance inductors. The IC includes at least one trench within a dielectric layer disposed on a substrate. The trench is conformally coated with a liner and seed layer, and includes an interconnect within. The interconnect includes a hard mask on the sidewalls of the interconnect.Type: ApplicationFiled: January 20, 2015Publication date: May 21, 2015Inventors: David A. DeMuynck, Zhong-Xiang He, Daniel R. Miga, Matthew D. Moon, Daniel S. Vanslette, Eric J. White
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Patent number: 9006703Abstract: Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.Type: GrantFiled: July 31, 2013Date of Patent: April 14, 2015Assignee: International Business Machines CorporationInventors: Shawn A. Adderly, Brian M. Czabaj, Daniel A. Delibac, Jeffrey P. Gambino, Matthew D. Moon, David C. Thomas
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Publication number: 20150035117Abstract: Aspects of the present invention relate to method for reducing lateral extrusion formed in semiconductor structures and semiconductor structures formed thereof. Various embodiments include a method for reducing lateral extrusion formed in semiconductor structures. The method can include removing a portion of a first lateral extrusion in an aluminum layer of the semiconductor structure, and determining a post-removal thickness of a dielectric layer positioned adjacent the aluminum layer. The post-removal thickness may be determined subsequent to the removing of the portion of the first lateral extrusion. The method can also include determining a difference between the post-removal thickness of the dielectric layer and a pre-removal thickness of the dielectric layer.Type: ApplicationFiled: July 31, 2013Publication date: February 5, 2015Applicant: International Business Machines CorporationInventors: Shawn A. Adderly, Brian M. Czabaj, Daniel A. Delibac, Jeffrey P. Gambino, Matthew D. Moon, David C. Thomas
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Publication number: 20150021743Abstract: Substrates (wafers) with uniform backside roughness and methods of manufacture are disclosed. The method includes forming a material on a backside of a wafer. The method further includes patterning the material to expose portions of the backside of the wafer. The method further includes roughening the backside of the wafer through the patterned material to form a uniform roughness.Type: ApplicationFiled: July 19, 2013Publication date: January 22, 2015Inventors: Shawn A. ADDERLY, Jeffrey P. GAMBINO, Max L. LIFSON, Matthew D. MOON, William J. MURPHY, Timothy D. SULLIVAN, David C. THOMAS