Abstract: A power meter for measuring power usage in a circuit includes preprocessor and a weighting network. The pre-processor is configured to receive toggle data for a number of power proxy signals in the circuit for a plurality of clock cycles of the circuit in a first time window. The power proxy signals and weighting values are determined automatically from simulated or emulated toggle data. For each power proxy signal, the pre-processor averages the toggle data over one or more clock cycles in one or more second time windows, within the first time window, to provide averaged toggle data, and outputs the averaged toggle data for each second time window. The weighting network is configured to combine the averaged toggle data from the power proxy signals, based on a set of weight values, to provide a measure of the power usage.

Abstract: A power meter for measuring power usage in a circuit includes preprocessor and a weighting network. The pre-processor is configured to receive toggle data for a number of power proxy signals in the circuit for a plurality of clock cycles of the circuit in a first time window. The power proxy signals and weighting values are determined automatically from simulated or emulated toggle data. For each power proxy signal, the pre-processor averages the toggle data over one or more clock cycles in one or more second time windows, within the first time window, to provide averaged toggle data, and outputs the averaged toggle data for each second time window. The weighting network is configured to combine the averaged toggle data from the power proxy signals, based on a set of weight values, to provide a measure of the power usage.

Abstract: A data processing apparatus contains branch prediction circuitry including a micro branch target buffer, a full branch target buffer and a global history buffer. The branch target buffer entries contain history data which indicates whether or not a number of the following blocks of program instructions, subsequent to and sequential to a block of program instruction identified by that branch target buffer entry containing a branch instruction, do themselves contain any branch instructions. If the history data indicates that the following blocks of program instructions do not contain branches, then the operation of the branch prediction circuitry is suppressed for these following blocks of program instructions so as to save energy.

Abstract: An apparatus comprises processing circuitry, an instruction cache, decoding circuitry to decode program instructions fetched from the cache to generate macro-operations to be processed by the processing circuitry, and predecoding circuitry to perform a predecoding operation on a block of program instructions fetched from a data store to generate predecode information to be stored to the cache with the block of instructions. In one example the predecoding operation comprises generating information on how many macro-operations are to generated by the decoding circuitry for a group of one or more program instructions. In another example the predecoding operation comprises generating information indicating whether at least one of a given subset of program instructions within the prefetched block is a branch instruction.

Abstract: An apparatus comprises processing circuitry, an instruction cache, decoding circuitry to decode program instructions fetched from the cache to generate macro-operations to be processed by the processing circuitry, and predecoding circuitry to perform a predecoding operation on a block of program instructions fetched from a data store to generate predecode information to be stored to the cache with the block of instructions. In one example the predecoding operation comprises generating information on how many macro-operations are to generated by the decoding circuitry for a group of one or more program instructions. In another example the predecoding operation comprises generating information indicating whether at least one of a given subset of program instructions within the prefetched block is a branch instruction.

Abstract: A data processing apparatus 2 contains branch prediction circuitry 10 including a micro branch target buffer 28, a full branch target buffer 30 and a global history buffer 32. The branch target buffer entries 40 contain history data 42, 44 which indicates whether or not a number of the following blocks of program instructions, subsequent to and sequential to a block of program instruction identified by that branch target buffer entry containing a branch instruction, do themselves contain any branch instructions. If the history data 42, 44 indicates that the following blocks of program instructions do not contain branches, then the operation of the branch prediction circuitry 28, 30, 32 is suppressed for these following blocks of program instructions so as to save energy.

Abstract: A data processing system is operable in a first state to use a first instruction set having a first instruction set encoding. The data processing system is also operable in a second state to use a second instruction set having a second instruction encoding. Conditional branch instructions provided within the two different instruction sets are arranged to use the same instruction encoding.

Abstract: A branch prediction mechanism includes a history value register storing a history value which is used to address into a history buffer from which a plurality of prediction values are read and stored into a prediction value store. The one or more prediction values to be used with a potential branch instruction are selected from the prediction values store using a multiplexer switched by a branch predicting portion of a fetch address. The history buffer is only read when the history value changes whereas the prediction values store is read each time a potential branch instruction is identified requiting a prediction value to be associated with it. The reduced duty cycle of the history buffer saves power.

Abstract: A branch target buffer is provided which maintains its entries across context switches within a virtually addressed system. Branch mispredictions are detected for individual entries within the branch target buffer and those individual entries are invalidated.

Abstract: A floating point unit 26 is provided with a register bank 38 comprising 32 registers that may be used as either vector registers V or scalar registers S. Data values are transferred between memory 30 and the registers within the register bank 38 using contiguous block memory access instructions. Vector processing instructions specify a sequence of processing operations to be performed upon data values within a sequence of registers. The register address is incremented between each operation by an amount controlled by a stride value. Accordingly, the register address can be incremented by values such as 0, 1, 2 or 4 between each iteration. This provides a mechanism for retaining block memory access instructions to contiguous memory addresses whilst supporting vector matrix and/or complex operations in which the data values needed for each iteration are not adjacent to one another in the memory 30.

Abstract: The data processing apparatus and method comprises an instruction decoder for decoding a vector instruction representing a sequence of data processing operations, and an execution unit comprising a plurality of pipelined stages for executing said sequence of data processing operations. The execution unit includes exception determination logic for determining, as each instruction enters a predetermined pipelined stage, whether that data processing operation is an exceptional operation matching predetermined exception criteria, the execution unit being arranged to halt processing of said exceptional operation. Further, an exception register is provided for storing exception attributes relating to said exceptional operation, said exception attributes indicating which data processing operation in said sequence has been determined to be said exceptional operation.

Abstract: A data processing apparatus and method is provided, the apparatus comprising an execution unit having a plurality of pipelined stages for executing instructions, such that a maximum of ‘n’ instructions can be being executed simultaneously within the execution unit. Further, a set of at least ‘n’ logical exception registers are provided, each exception register being capable of storing a number of exception attributes associated with an instruction for which an exception has been detected during execution by the execution unit. In the event of an exception being detected during execution of a first instruction, the execution unit is arranged to: (i) store in a first of said exception registers said exception attributes associated with said first instruction; and (ii) to continue executing any remaining instructions already in the pipelined stages at the time the exception was detected.