Patents by Inventor Matthew R. Poremba

Matthew R. Poremba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230205705
    Abstract: An approach provides indirect addressing support for PIM. Indirect PIM commands include address translation information that allows memory modules to perform indirect addressing. Processing logic in a memory module processes an indirect PIM command and retrieves, from a first memory location, a virtual address of a second memory location. The processing logic calculates a corresponding physical address for the virtual address using the address translation information included with the indirect PIM command and retrieves, from the second memory location, a virtual address of a third memory location. This process is repeated any number of times until one or more indirection stop criteria are satisfied. The indirection stop criteria stop the process when work has been completed normally or to prevent errors. Implementations include the processing logic in the memory module working in cooperation with a memory controller to perform indirect addressing.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Matthew R. Poremba, Alexandru Dutu, Sooraj Puthoor
  • Patent number: 11513801
    Abstract: An electronic device is described that handles control transfer instructions (CTIs) when executing instructions in program code. The electronic device has a processor that includes a branch prediction functional block and a sequential fetch logic functional block. The sequential fetch logic functional block determines, based on a record associated with a CTI, that a specified number of fetch groups of instructions that were previously determined to include no CTIs are to be fetched for execution in sequence following the CTI. When each of the specified number of fetch groups is fetched and prepared for execution, the sequential fetch logic prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that fetch group.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: November 29, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Adithya Yalavarti, John Kalamatianos, Matthew R. Poremba
  • Patent number: 11507519
    Abstract: A processing system selectively compresses cache lines at a cache or at a memory or encrypts cache lines at the memory based on evictions of entries mapping virtual-to-physical address translations from a translation lookaside buffer (TLB). Upon eviction of a TLB entry, the processing system identifies cache lines corresponding to the physical addresses of the evicted TLB entry and selectively compresses the cache lines to increase the effective storage capacity of the processing system or encrypts the cache lines to protect against vulnerabilities.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: November 22, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jagadish B. Kotra, Gabriel H. Loh, Matthew R. Poremba
  • Publication number: 20210149819
    Abstract: A processing system selectively compresses cache lines at a cache or at a memory or encrypts cache lines at the memory based on evictions of entries mapping virtual-to-physical address translations from a translation lookaside buffer (TLB). Upon eviction of a TLB entry, the processing system identifies cache lines corresponding to the physical addresses of the evicted TLB entry and selectively compresses the cache lines to increase the effective storage capacity of the processing system or encrypts the cache lines to protect against vulnerabilities.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 20, 2021
    Inventors: Jagadish B. KOTRA, Gabriel H. LOH, Matthew R. POREMBA
  • Publication number: 20200257623
    Abstract: An electronic device handles memory access requests for data in a memory. The electronic device includes a memory controller for the memory, a last-level cache memory, a request generator, and a predictor. The predictor determines a likelihood that a cache memory access request for data at a given address will hit in the last-level cache memory. Based on the likelihood, the predictor determines: whether a memory access request is to be sent by the request generator to the memory controller for the data in parallel with the cache memory access request being resolved in the last-level cache memory, and, when the memory access request is to be sent, a type of memory access request that is to be sent. When the memory access request is to be sent, the predictor causes the request generator to send a memory request of the type to the memory controller.
    Type: Application
    Filed: February 12, 2019
    Publication date: August 13, 2020
    Inventors: Jieming Yin, Yasuko Eckert, Matthew R. Poremba, Steven E. Raasch, Doug Hunt
  • Patent number: 10719441
    Abstract: An electronic device handles memory access requests for data in a memory. The electronic device includes a memory controller for the memory, a last-level cache memory, a request generator, and a predictor. The predictor determines a likelihood that a cache memory access request for data at a given address will hit in the last-level cache memory. Based on the likelihood, the predictor determines: whether a memory access request is to be sent by the request generator to the memory controller for the data in parallel with the cache memory access request being resolved in the last-level cache memory, and, when the memory access request is to be sent, a type of memory access request that is to be sent. When the memory access request is to be sent, the predictor causes the request generator to send a memory request of the type to the memory controller.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: July 21, 2020
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Jieming Yin, Yasuko Eckert, Matthew R. Poremba, Steven E. Raasch, Doug Hunt
  • Publication number: 20200081716
    Abstract: An electronic device is described that handles control transfer instructions (CTIs) when executing instructions in program code. The electronic device has a processor that includes a branch prediction functional block and a sequential fetch logic functional block. The sequential fetch logic functional block determines, based on a record associated with a CTI, that a specified number of fetch groups of instructions that were previously determined to include no CTIs are to be fetched for execution in sequence following the CTI. When each of the specified number of fetch groups is fetched and prepared for execution, the sequential fetch logic prevents corresponding accesses of the branch prediction functional block for acquiring branch prediction information for instructions in that fetch group.
    Type: Application
    Filed: September 10, 2018
    Publication date: March 12, 2020
    Inventors: Adithya Yalavarti, John Kalamatianos, Matthew R. Poremba
  • Patent number: 9367466
    Abstract: A type of conditional probability fetcher prefetches data, such as for a cache, from another memory by maintaining information relating to memory elements in a group of memory elements fetched from the second memory. The information may be an aggregate number of memory elements that have been fetched for different memory segments in the group. The information is maintained responsive to fetching one or more memory elements from a segment of memory elements in the group of memory elements. Prefetching one or more remaining memory elements in a particular segment of memory elements from the second memory into the first memory occurs when the information relating to the memory elements in the group of memory elements indicates that a prefetching condition has been satisfied.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: June 14, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthew R. Poremba, Gabriel H. Loh
  • Patent number: 9087561
    Abstract: Data caching methods and systems are provided. A method is provided for a hybrid cache system that dynamically changes modes of one or more cache rows of a cache between an un-split mode having a first tag field and a first data field to a split mode having a second tag field, a second data field being smaller than the first data field and a mapped page field to improve the cache access efficiency of a workflow being executed in a processor. A hybrid cache system is provided in which the cache is configured to operate one or more cache rows in an un-split mode or in a split mode. The system is configured to dynamically change modes of the cache rows from the un-split mode to the split mode to improve the cache access efficiency of a workflow being executed by the processor.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 21, 2015
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Matthew R. Poremba, Gabriel H. Loh
  • Patent number: 9053039
    Abstract: Data caching methods and systems are provided. The data cache method loads data into an installation cache and a cache (simultaneously or serially) and returns data from the installation cache when the data has not completely loaded into the cache. The data cache system includes a processor, a memory coupled to the processor, a cache coupled to the processor and the memory and an installation cache coupled to the processor and the memory. The system is configured to load data from the memory into the installation cache and the cache (simultaneously or serially) and return data from the installation cache to the processor when the data has not completely loaded into the cache.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: June 9, 2015
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Matthew R. Poremba, Gabriel H. Loh
  • Publication number: 20140229682
    Abstract: A type of conditional probability fetcher prefetches data, such as for a cache, from another memory by maintaining information relating to memory elements in a group of memory elements fetched from the second memory. The information may be an aggregate number of memory elements that have been fetched for different memory segments in the group. The information is maintained responsive to fetching one or more memory elements from a segment of memory elements in the group of memory elements. Prefetching one or more remaining memory elements in a particular segment of memory elements from the second memory into the first memory occurs when the information relating to the memory elements in the group of memory elements indicates that a prefetching condition has been satisfied.
    Type: Application
    Filed: February 13, 2013
    Publication date: August 14, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Matthew R. Poremba, Gabriel H. Loh
  • Publication number: 20140181389
    Abstract: Data caching methods and systems are provided. The data cache method loads data into an installation cache and a cache (simultaneously or serially) and returns data from the installation cache when the data has not completely loaded into the cache. The data cache system includes a processor, a memory coupled to the processor, a cache coupled to the processor and the memory and an installation cache coupled to the processor and the memory. The system is configured to load data from the memory into the installation cache and the cache (simultaneously or serially) and return data from the installation cache to the processor when the data has not completely loaded into the cache.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Matthew R. Poremba, Gabriel H. Loh
  • Publication number: 20140181387
    Abstract: Data caching methods and systems are provided. A method is provided for a hybrid cache system that dynamically changes modes of one or more cache rows of a cache between an un-split mode having a first tag field and a first data field to a split mode having a second tag field, a second data field being smaller than the first data field and a mapped page field to improve the cache access efficiency of a workflow being executed in a processor. A hybrid cache system is provided in which the cache is configured to operate one or more cache rows in an un-split mode or in a split mode. The system is configured to dynamically change modes of the cache rows from the un-split mode to the split mode to improve the cache access efficiency of a workflow being executed by the processor.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Matthew R. Poremba, Gabriel H. Loh