Abstract: A technique for managing processor cores within a multi-core central processing unit (CPU) provides efficient power and resource utilization over a wide workload range. The CPU comprises at least one core designed for low power operation and at least one core designed for high performance operation. For low workloads, the low power core executes the workload. For certain higher workloads, the high performance core executes the workload. For certain other workloads, the low power core and the high performance core both share execution of the workload. This technique advantageously enables efficient processing over a wider range of workloads than conventional systems.

Abstract: To preserve power and increase the overall efficiency of the CPU, the platform idle driver causes the power gate controller to cut power to the idle core. Such power gating is autonomous, i.e., the operating system and the other cores are not involved. In operation, the platform idle driver first prepares the core and the power gate controller for power gating the core. The platform idle driver then triggers the power gating. The power gate controller monitors interrupts released by the interrupt controller, and if any on the released interrupts are associated with the power gated core, the power gate controller resumes dispersing power to the core.

Abstract: A technique for managing processor cores within a multi-core central processing unit (CPU) provides efficient power and resource utilization over a wide workload range. The CPU comprises at least one core designed for low power operation and at least one core designed for high performance operation. For low workloads, the low power core executes the workload. For certain higher workloads, the high performance core executes the workload. For certain other workloads, the low power core and the high performance core both share execution of the workload. This technique advantageously enables efficient processing over a wider range of workloads than conventional systems.

Abstract: A first instance and a second instance of an oscillating circuit are each formed as part of an integrated circuit and are used to monitor degradation over time of one or more portions of the integrated circuit. The first instance of the oscillating circuit is configured to be coupled to a power source during normal operation of the integrated circuit and the second instance is configured to be decoupled from the power source. Over the lifetime of the integrated circuit, the first instance undergoes degradation from use while the second instance of the oscillating circuit remains unpowered, therefore experiencing essentially no use-related degradation. During a testing operation, the second instance can be used as a reference circuit that accurately quantifies use-related degradation of the first instance of the oscillating circuit and, by extension, one or more portions of the integrated circuit.

Abstract: To preserve power and increase the overall efficiency of the CPU, the platform idle driver causes the power gate controller to cut power to the idle core. Such power gating is autonomous, i.e., the operating system and the other cores are not involved. In operation, the platform idle driver first prepares the core and the power gate controller for power gating the core. The platform idle driver then triggers the power gating. The power gate controller monitors interrupts released by the interrupt controller, and if any on the released interrupts are associated with the power gated core, the power gate controller resumes dispersing power to the core.