Patents by Inventor Matthew Richard Miller

Matthew Richard Miller has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200333022
    Abstract: A fluid management system and method includes a thermal management system disposed within a housing that includes conduits extending between a source and a destination of a first fluid. The first fluid exchanges heat with cooling devices as the first fluid moves between the source and the destination. A fluid mixture including the first fluid and a second fluid, and an exhaust are generated responsive to the first fluid exchanging heat with the cooling devices. The exhaust directed toward an outlet of the housing. A separator assembly fluidly coupled with and disposed downstream of the thermal management system receives the fluid mixture and separates the first fluid from the second fluid. The first fluid is directed in a first direction out of the separator assembly and the second fluid is directed toward the outlet to be combined with the exhaust.
    Type: Application
    Filed: April 17, 2020
    Publication date: October 22, 2020
    Inventors: Matthew J. Chatham, Benjamin Richard Kundman, Andrew T. Miller
  • Publication number: 20200321479
    Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.
    Type: Application
    Filed: March 9, 2020
    Publication date: October 8, 2020
    Applicant: Futurewei Technologies, Inc.
    Inventors: Brian Creed, Lawrence E. Connell, Kent Jaeger, Matthew Richard Miller
  • Patent number: 10771028
    Abstract: An apparatus comprises a plurality of selectable gain stages connected in parallel between a first bias voltage and ground, wherein each selectable gain stage comprises an amplification portion and a current steering portion, and wherein the current steering portion comprises a first selectable signal path connected between an output of the amplification portion and a signal output terminal, and a second selectable signal path connected between the output of the amplification portion and ground through a shunt device.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: September 8, 2020
    Assignee: FutureWei Technologies, Inc.
    Inventors: William Roeckner, Terrie McCain, Matthew Richard Miller, Lawrence E. Connell
  • Patent number: 10715195
    Abstract: The disclosure relates to technology for an apparatus having a current conveyer comprising a first stage having a first differential input, and a second stage having a second differential input. The first and second stages are configured to operate in a push-pull mode to provide an output signal at a current conveyer output between the first stage and the second stage. The apparatus has a first frequency mixer configured to generate a first mixer signal based on an input signal and an oscillator signal having a first frequency. The first frequency mixer is configured to provide the first mixer signal to the first differential input. The apparatus has a second frequency mixer configured to generate a second mixer signal based on the input signal and a second oscillator signal having the first frequency. The second frequency mixer is configured to provide the second mixer signal to the second differential input.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: July 14, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventors: Matthew Richard Miller, Brian Creed, Terrie McCain
  • Patent number: 10586878
    Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: March 10, 2020
    Assignee: Futurewei Technologies, Inc.
    Inventors: Brian Creed, Lawrence Connell, Kent Jaeger, Matthew Richard Miller
  • Publication number: 20190386694
    Abstract: The disclosure relates to technology for an apparatus having a current conveyer comprising a first stage having a first differential input, and a second stage having a second differential input. The first and second stages are configured to operate in a push-pull mode to provide an output signal at a current conveyer output between the first stage and the second stage. The apparatus has a first frequency mixer configured to generate a first mixer signal based on an input signal and an oscillator signal having a first frequency. The first frequency mixer is configured to provide the first mixer signal to the first differential input. The apparatus has a second frequency mixer configured to generate a second mixer signal based on the input signal and a second oscillator signal having the first frequency. The second frequency mixer is configured to provide the second mixer signal to the second differential input.
    Type: Application
    Filed: June 13, 2018
    Publication date: December 19, 2019
    Applicant: Futurewei Technologies, Inc.
    Inventors: Matthew Richard Miller, Brian Creed, Terrie McCain
  • Publication number: 20190372538
    Abstract: An apparatus comprises a plurality of selectable gain stages connected in parallel between a first bias voltage and ground, wherein each selectable gain stage comprises an amplification portion and a current steering portion, and wherein the current steering portion comprises a first selectable signal path connected between an output of the amplification portion and a signal output terminal, and a second selectable signal path connected between the output of the amplification portion and ground through a shunt device.
    Type: Application
    Filed: October 26, 2018
    Publication date: December 5, 2019
    Inventors: William Roeckner, Terrie McCain, Matthew Richard Miller, Lawrence E. Connell
  • Publication number: 20180090627
    Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.
    Type: Application
    Filed: December 4, 2017
    Publication date: March 29, 2018
    Inventors: Brian Creed, Lawrence Connell, Kent Jaeger, Matthew Richard Miller
  • Patent number: 9837555
    Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: December 5, 2017
    Assignee: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Brian Creed, Lawrence Connell, Kent Jaeger, Matthew Richard Miller
  • Patent number: 9729126
    Abstract: Method and implementation of gain-bandwidth product (GWB) tuning are disclosed. In an embodiment an operational amplifier (opamp) includes an input stage of the opamp including a differential device pair coupled to a tail device and configured to be responsive to a differential input signal for conducting a first current and an output stage of the opamp including a class AB interface stage circuit and a pair of output devices connected to the class AB interface stage circuit, wherein a first constant gm bias circuit is coupled to an input terminal of the class AB interface stage circuit.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: August 8, 2017
    Assignee: Futurewei Technologies, Inc.
    Inventors: Homero Luz Guimaraes, Matthew Richard Miller
  • Publication number: 20170126207
    Abstract: Method and implementation of gain-bandwidth product (GWB) tuning are disclosed. In an embodiment an operational amplifier (opamp) includes an input stage of the opamp including a differential device pair coupled to a tail device and configured to be responsive to a differential input signal for conducting a first current and an output stage of the opamp including a class AB interface stage circuit and a pair of output devices connected to the class AB interface stage circuit, wherein a first constant gm bias circuit is coupled to an input terminal of the class AB interface stage circuit.
    Type: Application
    Filed: October 28, 2015
    Publication date: May 4, 2017
    Inventors: Homero Luz Guimaraes, Matthew Richard Miller
  • Publication number: 20160308073
    Abstract: Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.
    Type: Application
    Filed: April 15, 2015
    Publication date: October 20, 2016
    Inventors: Brian Creed, Lawrence Connell, Kent Jaeger, Matthew Richard Miller
  • Patent number: 8952748
    Abstract: An embodiment integrated circuit includes a first capacitive element including a first metal-oxide-semiconductor (MOS) capacitor and a second capacitive element coupled in parallel with the first capacitive element, where the second capacitive element includes a second MOS capacitor. Also, the integrated circuit includes a third capacitive element coupled in parallel with the first capacitive element and the second capacitive element, where the third capacitive element includes a first metal-insulator-metal (MIM) capacitor and a fourth capacitive element coupled in parallel with the first capacitive element, the second capacitive element, and the third capacitive element, where the fourth capacitive element includes a second MIM capacitor.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: February 10, 2015
    Assignee: FutureWei Technologies, Inc.
    Inventors: Homero Guimaraes, Matthew Richard Miller
  • Patent number: 8928407
    Abstract: A system includes a first variable gain amplifier configured to receive an input signal and a first down-mixer coupled to the first variable gain amplifier. Also, the system includes a first current conveyor coupled to the first down mixer, where the first current conveyor includes a first cascode and a second cascode coupled to the first cascode. Additionally, the system includes a first channel filter coupled to the first current conveyor and a second variable gain amplifier coupled to the first channel filter.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: January 6, 2015
    Assignee: Futurewei Technologies, Inc.
    Inventors: Matthew Richard Miller, Terrie McCain
  • Publication number: 20140266408
    Abstract: An embodiment integrated circuit includes a first capacitive element including a first metal-oxide-semiconductor (MOS) capacitor and a second capacitive element coupled in parallel with the first capacitive element, where the second capacitive element includes a second MOS capacitor. Also, the integrated circuit includes a third capacitive element coupled in parallel with the first capacitive element and the second capacitive element, where the third capacitive element includes a first metal-insulator-metal (MIM) capacitor and a fourth capacitive element coupled in parallel with the first capacitive element, the second capacitive element, and the third capacitive element, where the fourth capacitive element includes a second MIM capacitor.
    Type: Application
    Filed: April 29, 2013
    Publication date: September 18, 2014
    Applicant: FutureWei Technologies, Inc.
    Inventors: Homero Guimaraes, Matthew Richard Miller
  • Publication number: 20140253233
    Abstract: A system includes a first variable gain amplifier configured to receive an input signal and a first down-mixer coupled to the first variable gain amplifier. Also, the system includes a first current conveyor coupled to the first down mixer, where the first current conveyor includes a first cascode and a second cascode coupled to the first cascode. Additionally, the system includes a first channel filter coupled to the first current conveyor and a second variable gain amplifier coupled to the first channel filter.
    Type: Application
    Filed: March 11, 2013
    Publication date: September 11, 2014
    Applicant: FUTUREWEI TECHNOLOGIES, INC.
    Inventors: Matthew Richard Miller, Terrie McCain