Patents by Inventor Matthew W. Copel

Matthew W. Copel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130280901
    Abstract: A non-transitory computer readable medium encoded with a program for fabricating a gate stack for a transistor is disclosed. The program includes instructions configured to perform a method. The method includes forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer.
    Type: Application
    Filed: June 24, 2013
    Publication date: October 24, 2013
    Inventors: Takashi ANDO, Kisik CHOI, Matthew W. COPEL, Richard A. HAIGHT
  • Patent number: 8564066
    Abstract: A method of fabricating a gate stack for a transistor includes forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: October 22, 2013
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Kisik Choi, Matthew W. Copel, Richard A. Haight
  • Patent number: 8518766
    Abstract: A field effect transistor (FET) includes a body region and a source region disposed at least partially in the body region. The FET also includes a drain region disposed at least partially in the body region and a molybdenum oxynitride (MoNO) gate. The FET also includes a dielectric having a high dielectric constant (k) disposed between the body region and the MoNO gate.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: Nestor A. Bojarczuk, Michael P. Chudzik, Matthew W. Copel, Supratik Guha, Richard A. Haight, Vijay Narayanan, Martin P. O'Boyle, Vamsi K. Paruchuri
  • Publication number: 20120270385
    Abstract: A field effect transistor (FET) includes a body region and a source region disposed at least partially in the body region. The FET also includes a drain region disposed at least partially in the body region and a molybdenum oxynitride (MoNO) gate. The FET also includes a dielectric having a high dielectric constant (k) disposed between the body region and the MoNO gate.
    Type: Application
    Filed: June 28, 2012
    Publication date: October 25, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nestor A. Bojarczuk, Michael P. Chudzik, Matthew W. Copel, Supratik Guha, Richard A. Haight, Vijay Narayanan, Martin P. O'Boyle, Vamsi K. Paruchuri
  • Patent number: 8193051
    Abstract: The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride.
    Type: Grant
    Filed: March 14, 2011
    Date of Patent: June 5, 2012
    Assignee: International Business Machines Corporation
    Inventors: Nestor A. Bojarczuk, Jr., Cyril Cabral, Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
  • Patent number: 8134150
    Abstract: A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: March 13, 2012
    Assignee: International Business Machines Corporation
    Inventors: David B. Mitzi, Matthew W. Copel
  • Publication number: 20110309449
    Abstract: A method of fabricating a gate stack for a transistor includes forming a high dielectric constant layer on a semiconductor layer. A metal layer is formed on the high dielectric constant layer. A silicon containing layer is formed over the metal layer. An oxidized layer incidentally forms during the silicon containing layer formation and resides on the metal layer beneath the silicon containing layer. The silicon containing layer is removed. The oxidized layer residing on the metal layer is removed after removing the silicon containing layer.
    Type: Application
    Filed: June 18, 2010
    Publication date: December 22, 2011
    Applicant: International Business Machines Corporation
    Inventors: TAKASHI ANDO, Kisik Choi, Matthew W. Copel, Richard A. Haight
  • Patent number: 8053772
    Abstract: A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: David B. Mitzi, Matthew W. Copel
  • Publication number: 20110240932
    Abstract: A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.
    Type: Application
    Filed: May 20, 2011
    Publication date: October 6, 2011
    Applicant: International Business Machines Corporation
    Inventors: David B. Mitzi, Matthew W. Copel
  • Patent number: 7999255
    Abstract: A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: August 16, 2011
    Assignee: International Business Machines Corporation
    Inventors: David B. Mitzi, Matthew W. Copel
  • Patent number: 7999323
    Abstract: The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: August 16, 2011
    Assignee: International Business Machines Corporation
    Inventors: Eduard A. Cartier, Matthew W. Copel, Bruce B. Doris, Rajarao Jammy, Young-Hee Kim, Barry P. Linder, Vijay Narayanan, Vamsi K. Paruchuri, Keith Kwong Hon Wong
  • Publication number: 20110165767
    Abstract: The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride.
    Type: Application
    Filed: March 14, 2011
    Publication date: July 7, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nestor A. Bojarczuk, JR., Cyril Cabral, JR., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
  • Patent number: 7960726
    Abstract: A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.
    Type: Grant
    Filed: August 27, 2009
    Date of Patent: June 14, 2011
    Assignee: International Business Machines Corporation
    Inventors: David B. Mitzi, Matthew W. Copel
  • Patent number: 7943458
    Abstract: Methods of forming complementary metal oxide semiconductor (CMOS) structures with tunable threshold voltages are provided. The methods disclose a technique of obtaining selective placement of threshold voltage adjusting materials on a semiconductor substrate by using a block mask prior to deposition of the threshold voltage adjusting materials. The block mask is subsequently removed to obtain a patterned threshold voltage adjusting material on the semiconductor substrate. The methods are material independent and can be used in sequence for both nFET threshold voltage adjusting materials and pFET threshold voltage adjusting materials.
    Type: Grant
    Filed: October 6, 2009
    Date of Patent: May 17, 2011
    Assignee: International Business Machines Corporation
    Inventors: Hemanth Jagannathan, Sivananda K. Kanakasabapathy, Matthew W. Copel
  • Patent number: 7928514
    Abstract: The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: April 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Nestor A. Bojarczuk, Jr., Cyril Cabral, Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
  • Publication number: 20110081754
    Abstract: Methods of forming complementary metal oxide semiconductor (CMOS) structures with tunable threshold voltages are provided. The methods disclose a technique of obtaining selective placement of threshold voltage adjusting materials on a semiconductor substrate by using a block mask prior to deposition of the threshold voltage adjusting materials. The block mask is subsequently removed to obtain a patterned threshold voltage adjusting material on the semiconductor substrate. The methods are material independent and can be used in sequence for both nFET threshold voltage adjusting materials and pFET threshold voltage adjusting materials.
    Type: Application
    Filed: October 6, 2009
    Publication date: April 7, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hemanth Jagannathan, Sivananda K. Kanakasabapathy, Matthew W. Copel
  • Publication number: 20110042759
    Abstract: A field effect transistor (FET) includes a body region and a source region disposed at least partially in the body region. The FET also includes a drain region disposed at least partially in the body region and a molybdenum oxynitride (MoNO) gate. The FET also includes a dielectric having a high dielectric constant (k) disposed between the body region and the MoNO gate.
    Type: Application
    Filed: August 21, 2009
    Publication date: February 24, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Nestor A. Bojarczuk, Michael P. Chudzik, Matthew W. Copel, Supratik Guha, Richard A. Haight, Vijay Narayanan, Martin P. O'Boyle, Vamsi K. Paruchuri
  • Patent number: 7858500
    Abstract: A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.
    Type: Grant
    Filed: April 4, 2008
    Date of Patent: December 28, 2010
    Assignee: International Business Machines Corporation
    Inventors: Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Paul C. Jamison, Rajarao Jammy, Barry P. Linder, Vijay Narayanan
  • Patent number: 7745278
    Abstract: A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.
    Type: Grant
    Filed: September 16, 2008
    Date of Patent: June 29, 2010
    Assignee: International Business Machines Corporation
    Inventors: Nestor A. Bojarczuk, Jr., Cyril Cabral, Jr., Eduard A. Cartier, Matthew W. Copel, Martin M. Frank, Evgeni P. Gousev, Supratik Guha, Rajarao Jammy, Vijay Narayanan, Vamsi K. Paruchuri
  • Publication number: 20100040891
    Abstract: A method of depositing a film of a metal chalcogenide including the steps of: contacting an isolated hydrazinium-based precursor of a metal chalcogenide and a solvent having therein a solubilizing additive to form a solution of a complex thereof; applying the solution of the complex onto a substrate to produce a coating of the solution on the substrate; removing the solvent from the coating to produce a film of the complex on the substrate; and thereafter annealing the film of the complex to produce a metal chalcogenide film on the substrate. Also provided is a process for preparing an isolated hydrazinium-based precursor of a metal chalcogenide as well as a thin-film field-effect transistor device using the metal chalcogenides as the channel layer.
    Type: Application
    Filed: August 27, 2009
    Publication date: February 18, 2010
    Applicant: International Business Machines Corporation
    Inventors: David B. Mitzi, Matthew W. Copel