Patents by Inventor Maureen Anne Delaney

Maureen Anne Delaney has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10223125
    Abstract: An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey Carl Brownscheidle, Sundeep Chadha, Maureen Anne Delaney, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto
  • Publication number: 20180336038
    Abstract: An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.
    Type: Application
    Filed: July 30, 2018
    Publication date: November 22, 2018
    Inventors: Jeffrey Carl Brownscheidle, Sundeep Chadha, Maureen Anne Delaney, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto
  • Patent number: 10133581
    Abstract: An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey Carl Brownscheidle, Sundeep Chadha, Maureen Anne Delaney, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto
  • Publication number: 20160202990
    Abstract: An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.
    Type: Application
    Filed: January 13, 2015
    Publication date: July 14, 2016
    Inventors: Jeffrey Carl Brownscheidle, Sundeep Chadha, Maureen Anne Delaney, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto
  • Publication number: 20160202992
    Abstract: A method of processing using an execution slice circuit including multiple parallel instruction execution slices provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The method also detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.
    Type: Application
    Filed: May 28, 2015
    Publication date: July 14, 2016
    Inventors: Jeffrey Carl Brownscheidle, Sundeep Chadha, Maureen Anne Delaney, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto
  • Patent number: 8489863
    Abstract: An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store (IDS). The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update.
    Type: Grant
    Filed: April 19, 2012
    Date of Patent: July 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: James Wilson Bishop, Mary Douglass Brown, Jeffrey Carl Brownscheidle, Robert Allen Cordes, Maureen Anne Delaney, Jafar Nahidi, Dung Quoc Nguyen, Joel Abraham Silberman
  • Patent number: 8380964
    Abstract: An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store IDS. The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: James Wilson Bishop, Mary Douglass Brown, Jeffrey Carl Brownscheidle, Robert Allen Cordes, Maureen Anne Delaney, Jafar Nahidi, Dung Quoc Nguyen, Joel Abraham Silberman
  • Publication number: 20120260069
    Abstract: An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store (IDS). The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update.
    Type: Application
    Filed: April 19, 2012
    Publication date: October 11, 2012
    Applicants: IBM Corporation, International Business Machines Corporation
    Inventors: James Wilson Bishop, Mary Douglass Brown, Jeffrey Carl Brownscheidle, Robert Allen Cordes, Maureen Anne Delaney, Jafar Nahidi, Dung Quoc Nguyen, Joel Abraham Silberman
  • Publication number: 20110185159
    Abstract: An information handling system includes a processor with an instruction issue queue (IQ) that may perform age tracking operations. The issue queue IQ maintains or stores instructions that may issue out-of-order in an internal data store IDS. The IDS organizes instructions in a queue position (QPOS) addressing arrangement. An age matrix of the IQ maintains a record of relative instruction aging for those instructions within the IDS. The age matrix updates latches or other memory cell data to reflect the changes in IDS instruction ages during a dispatch operation into the IQ. During dispatch of one or more instructions, the age matrix may update only those latches that require data change to reflect changing IDS instruction ages. The age matrix employs row and column data and clock controls to individually update those latches requiring update.
    Type: Application
    Filed: April 3, 2009
    Publication date: July 28, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James Wilson Bishop, Mary Douglass Brown, Jeffrey Carl Brownscheidle, Robert Allen Cordes, Maureen Anne Delaney, Jafar Nahidi, Dung Quoc Nguyen, Joel Abraham Silberman
  • Patent number: 7663963
    Abstract: An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: February 16, 2010
    Assignee: International Business Machines Corporation
    Inventors: Sam Gat-Shang Chu, Maureen Anne Delaney, Saiful Islam, Dung Quoc Nguyen, Jafar Nahidi
  • Publication number: 20080239860
    Abstract: An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
    Type: Application
    Filed: June 6, 2008
    Publication date: October 2, 2008
    Applicant: International Business Machines Corporation
    Inventors: Sam Gat-Shang Chu, Maureen Anne Delaney, Saiful Islam, Dung Quoc Nguyen, Jafar Nahidi
  • Patent number: 7400548
    Abstract: Reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file is provided. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. A mechanism to write the consecutive entries by only having a 4 to 16 decode of one address is also provided. In addition, a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address is provided. The two read word lines are used to access the two read ports of the entries in the sub-arrays.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: July 15, 2008
    Assignee: International Business Machines Corporation
    Inventors: Sam Gat-Shang Chu, Maureen Anne Delaney, Saiful Islam, Dung Quoc Nguyen, Jafar Nahidi
  • Patent number: 7243209
    Abstract: An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.
    Type: Grant
    Filed: January 27, 2005
    Date of Patent: July 10, 2007
    Assignee: International Business Machines Corporation
    Inventors: Sam Gat-Shang Chu, Maureen Anne Delaney, Saiful Islam, Jafar Nahidi, Dung Quoc Nguyen