Patents by Inventor Maurice B. Steinman
Maurice B. Steinman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230342325Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a non-PCIe protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a non-PCIe format, encapsulating the non-PCIe format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.Type: ApplicationFiled: June 30, 2023Publication date: October 26, 2023Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Gordon Caruk, Maurice B. Steinman, Gerald R. Talbot, Joseph D. Macri
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Patent number: 11726915Abstract: A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.Type: GrantFiled: March 17, 2020Date of Patent: August 15, 2023Assignee: Advanced Micro Devices, Inc.Inventors: Yasuko Eckert, Maurice B. Steinman, Steven Raasch
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Patent number: 11693813Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a Gen-Z protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.Type: GrantFiled: May 30, 2019Date of Patent: July 4, 2023Assignees: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Gordon Caruk, Maurice B. Steinman, Gerald R. Talbot, Joseph D. Macri
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Patent number: 11275829Abstract: An apparatus includes an external device for causing messages to be transmitted with local traffic between internal blocks of a host system-on-chip (SoC) via a network on chip (NoC) in the host SoC, the transmitted messages including one or more memory requests directed to a memory of the host SoC, violating a traffic policy for a first time interval by transmitting a number of messages that exceeds a maximum threshold of for the first time interval, where the SoC monitors an amount of external traffic from an untrusted device transmitted over the NoC over a set of one or more time intervals including the first time interval, and in response to detection of the violation by the host SoC, reducing an amount of traffic transmitted via the NoC. The apparatus also includes an external processor link for transmitting the messages from the external device to the host SoC.Type: GrantFiled: April 23, 2020Date of Patent: March 15, 2022Assignee: Advanced Micro Devices, Inc.Inventors: Gabriel H Loh, Maurice B Steinman
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Publication number: 20200278930Abstract: A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.Type: ApplicationFiled: March 17, 2020Publication date: September 3, 2020Inventors: Yasuko ECKERT, Maurice B. STEINMAN, Steven RAASCH
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Publication number: 20200257796Abstract: A host system-on-chip (SoC) includes a network on chip (NoC) for transmitting local traffic between internal blocks of the SoC, an external processor link for receiving messages at the host SoC from an untrusted device. A traffic controller in the host SoC that is coupled with the external processor link monitors an amount of external traffic from the untrusted device over a set of one or more time intervals, detects a violation of a traffic policy based on the amount of external traffic, and in response to detecting the violation, reduces traffic in the NoC resulting from the messages from the untrusted device.Type: ApplicationFiled: April 23, 2020Publication date: August 13, 2020Inventors: Gabriel H. Loh, Maurice B. Steinman
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Publication number: 20200192853Abstract: A link controller includes a Peripheral Component Interconnect Express (PCIe) physical layer circuit for coupling to a communication link and providing a data path over the communication link, a first data link layer controller which operates according to a PCIe protocol, and a second data link layer controller which operates according to a Gen-Z protocol. A multiplexer-demultiplexer selectively connects both data link layer controllers to the PCIe physical layer circuit. A protocol translation circuit is coupled between the multiplexer-demultiplexer and the second data link layer controller, the protocol translation circuit receiving traffic data from the second data link layer controller in a Gen-Z format, encapsulating the Gen-Z format in a PCIe format, and passing traffic data to the multiplexer-demultiplexer circuit.Type: ApplicationFiled: May 30, 2019Publication date: June 18, 2020Applicants: ATI Technologies ULC, Advanced Micro Devices, Inc.Inventors: Gordon Caruk, Maurice B. Steinman, Gerald R. Talbot, Joseph D. Macri
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Patent number: 10671722Abstract: A host system-on-chip (SoC) includes a network on chip (NoC) for transmitting local traffic between internal blocks of the SoC, an external processor link for receiving messages at the host SoC from an untrusted device. A traffic controller in the host SoC that is coupled with the external processor link monitors an amount of external traffic from the untrusted device over a set of one or more time intervals, detects a violation of a traffic policy based on the amount of external traffic, and in response to detecting the violation, reduces traffic in the NoC resulting from the messages from the untrusted device.Type: GrantFiled: August 6, 2016Date of Patent: June 2, 2020Assignee: Advanced Micro Devices, Inc.Inventors: Gabriel H Loh, Maurice B Steinman
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Patent number: 10635588Abstract: A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.Type: GrantFiled: June 5, 2018Date of Patent: April 28, 2020Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Yasuko Eckert, Maurice B. Steinman, Steven Raasch
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Publication number: 20190370174Abstract: A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.Type: ApplicationFiled: June 5, 2018Publication date: December 5, 2019Inventors: Yasuko ECKERT, Maurice B. STEINMAN, Steven RAASCH
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Patent number: 10223162Abstract: Systems, apparatuses, and methods for tracking system resource utilization of guest virtual machines (VMs). Counters may be maintained to track resource utilization of different system resources by different guest VMs executing on the system. When a guest VM initiates execution, stored values may be loaded into the resource utilization counters. While the guest VM executes, the counters may track the resource utilization of the guest VM. When the guest VM terminates execution, the counter values may be written to a virtual machine control block (VMCB) corresponding to the guest VM. Scaling factors may be applied to the counter values to normalize the values prior to writing the values to the VMCB. A cloud computing environment may utilize the tracking mechanisms to guarantee resource utilization levels in accordance with users' service level agreements.Type: GrantFiled: April 13, 2016Date of Patent: March 5, 2019Assignee: Advanced Micro Devices, Inc.Inventors: Michael T. Clark, Jay Fleischman, Thaddeus S. Fortenberry, Maurice B. Steinman
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Publication number: 20180039777Abstract: A host system-on-chip (SoC) includes a network on chip (NoC) for transmitting local traffic between internal blocks of the SoC, an external processor link for receiving messages at the host SoC from an untrusted device. A traffic controller in the host SoC that is coupled with the external processor link monitors an amount of external traffic from the untrusted device over a set of one or more time intervals, detects a violation of a traffic policy based on the amount of external traffic, and in response to detecting the violation, reduces traffic in the NoC resulting from the messages from the untrusted device.Type: ApplicationFiled: August 6, 2016Publication date: February 8, 2018Inventors: Gabriel H. Loh, Maurice B. Steinman
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Publication number: 20170031719Abstract: Systems, apparatuses, and methods for tracking system resource utilization of guest virtual machines (VMs). Counters may be maintained to track resource utilization of different system resources by different guest VMs executing on the system. When a guest VM initiates execution, stored values may be loaded into the resource utilization counters. While the guest VM executes, the counters may track the resource utilization of the guest VM. When the guest VM terminates execution, the counter values may be written to a virtual machine control block (VMCB) corresponding to the guest VM. Scaling factors may be applied to the counter values to normalize the values prior to writing the values to the VMCB. A cloud computing environment may utilize the tracking mechanisms to guarantee resource utilization levels in accordance with users' service level agreements.Type: ApplicationFiled: April 13, 2016Publication date: February 2, 2017Inventors: Michael T. Clark, Jay Fleischman, Thaddeus S. Fortenberry, Maurice B. Steinman
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Patent number: 9423847Abstract: A processor includes a processor core and a power management controller operable to receive a timer event, store the timer event, generate a hardware system sleep command to enter a hardware system sleep state, and restore the timer event upon exiting from the hardware system sleep state.Type: GrantFiled: December 20, 2011Date of Patent: August 23, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Krishna S Bernucho, Maurice B Steinman, Ming L. So, Mom-Eng Ng, Xiaogang Zheng, Paul Blinzer, Francisco L Duran, Walter G. Fry, Ali Ibrahim, Andrew W. Lueck, Dan P Shimizu, Gary H. Simpson, Laura M. Smith
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Patent number: 9417679Abstract: Various computing devices and methods of managing the power consumption thereby are disclosed. In one aspect, a method of managing power consumption of a computing device that has a battery is provided. The method includes cycling the computing device between a connected standby active state and a connected standby idle state. The duration of the connected standby idle state is set based at least in part on a charge level of the battery.Type: GrantFiled: November 12, 2012Date of Patent: August 16, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Greg Sadowski, Alexander J. Branover, Maurice B. Steinman
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Patent number: 9261949Abstract: An apparatus and method for dynamically adjusting power limits for processing nodes and other components, such as peripheral interfaces, is disclosed. The apparatus includes multiple processing nodes and other components, and further includes a power management unit configured to set a first frequency limit for at least one of the processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold. Initial power limits are set below guard-band power limits for components that do not have reliable reporting of power consumption or for cost or power saving reasons. The amount of throttling of processing nodes is used to adjust the power limits for the processing nodes and these components.Type: GrantFiled: May 8, 2013Date of Patent: February 16, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Alexander J. Branover, Ashish Jain, Ann M. Ling, Maurice B. Steinman
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Patent number: 9043625Abstract: A power controller can set the power state of a processor bridge based on which processor modules are in a communicative state. In addition, for a power state where selected processor modules are expected to be non-communicative, the power controller can set the supplied voltage to have a reduced voltage guard band as compared to other power states. These power management techniques can reduce the power consumed by the processor.Type: GrantFiled: April 13, 2012Date of Patent: May 26, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Maurice B. Steinman, Alexander J. Branover, Denis J. Foley, Ljubisa Bajic
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Patent number: 9021209Abstract: A processing node tracks probe activity level associated with its cache. The processing node and/or processing system further predicts an idle duration. If the probe activity level increases above a threshold probe activity level, and the idle duration prediction is above a threshold idle duration threshold, the processing node flushes its cache to prevent probes to the cache. If the probe activity level is above the threshold probe activity level but the predicted idle duration is too short, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests.Type: GrantFiled: February 8, 2010Date of Patent: April 28, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Alexander Branover, Maurice B. Steinman
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Patent number: 8966305Abstract: Techniques are disclosed relating to managing power consumption and latencies for entry and exit of idle power states. In one embodiment, a processor includes a processing core configured to operate in a plurality of power states (e.g., C-states) that includes an operating power state and at least one idle power state. The processing core is also configured to operate in a plurality of performance states. The processor further includes a power management unit configured to receive a request from the processing core to enter the at least one idle power state. The power management unit is configured to select a first of the plurality of performance states (e.g., P-states) based on the requested idle power state. In one embodiment, the power management unit is further configured to cause the processing core to transition into the selected first performance state prior to entering the requested idle power state.Type: GrantFiled: June 30, 2011Date of Patent: February 24, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Alexander Branover, Maurice B. Steinman, John P. Petry
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Patent number: 8959372Abstract: An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.Type: GrantFiled: June 17, 2013Date of Patent: February 17, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Alexander Branover, Maurice B Steinman, William L Bircher