Patents by Inventor Maurice O. Othieno

Maurice O. Othieno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8163643
    Abstract: A semiconductor device is disclosed that has a die and a substrate having a die attachment area with a perimeter. A layer of solder connects the substrate and the die, the solder layer having at least one vent channel connected to the perimeter of the die attachment area, wherein the maximum distance from any point in the solder layer to the nearest free surface of the solder at a vent channel or at the perimeter of the die is less than the distance from the center of the die to the nearest edge of the die.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: April 24, 2012
    Assignee: Linear Technology Corporation
    Inventors: Maurice O. Othieno, Ramaswamy Ranganathan, Frederick E. Beville, David A. Pruitt, William D. Griffitts
  • Patent number: 8129759
    Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.
    Type: Grant
    Filed: November 24, 2009
    Date of Patent: March 6, 2012
    Assignee: LSI Logic Corporation
    Inventors: Maurice O. Othieno, Chok J. Chia, Amar J. Amin
  • Publication number: 20100067207
    Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.
    Type: Application
    Filed: November 24, 2009
    Publication date: March 18, 2010
    Applicant: LSI CORPORATION
    Inventors: Maurice O. Othieno, Chok J. Chia, Amar J. Amin
  • Patent number: 7646091
    Abstract: Embodiments of the invention include a semiconductor integrated circuit package that includes a substrate which can have an integrated circuit die attached thereto. The package includes a dedicated high-speed ground plane that is electrically isolated from the ground plane used to ground the low speed circuitry of the package.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: January 12, 2010
    Assignee: LSI Corporation
    Inventors: Maurice O. Othieno, Chok J. Chia, Amar J. Amin
  • Patent number: 7436060
    Abstract: A semiconductor integrated circuit package incorporating a preformed one-piece mold cap and heatspreader assembly is disclosed. One implementation includes a substrate with a die attached to the substrate. The die is electrically connected with electrical connections formed on the substrate using bonding wires. A preformed one-piece integrated mold cap and heatspreader assembly attached to the substrate to enclose at least a portion of the bonding wires and the die. Methods of assembling semiconductor integrated circuit packages using a preformed one-piece integrated mold cap and heatspreader assembly are also disclosed.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: October 14, 2008
    Assignee: LSI Corporation
    Inventors: Pradip Patel, Maurice O. Othieno, Manickam Thavarajah, Severino A. Legaspi, Jr.
  • Patent number: 7420809
    Abstract: An integrated circuit (IC) package comprises a package substrate, an IC die mounted on the package substrate, a wire bond electrically connecting the IC die and the package substrate, and a heat spreader mounted on the package substrate. The heat spreader comprises a hole through a portion thereof. The IC die and the wire bond are disposed substantially between the heat spreader and the package substrate.
    Type: Grant
    Filed: June 22, 2004
    Date of Patent: September 2, 2008
    Assignee: LSI Corporation
    Inventors: Hong T. Lim, Maurice O. Othieno, Qwai H. Low
  • Patent number: 7327043
    Abstract: A routing pattern for high speed signals for a package substrate. Electrically conductive bond fingers are disposed on a first surface of the package substrate. The first surface is adapted to receive an integrated circuit in an attachment zone, and the bond fingers are disposed in at least two substantially concentric rings around the attachment zone. The bond fingers of the innermost ring of bond fingers are all routed to electrically conductive first traces disposed on a first layer of the package substrate. The bond fingers other that those on the innermost ring of bond fingers are all routed to electrically conductive second traces disposed on a separate second layer of the package substrate. The package substrate has electrically conductive traces on only the first layer and the second layer. Electrically conductive contacts are disposed on a substantially opposing second surface.
    Type: Grant
    Filed: August 17, 2005
    Date of Patent: February 5, 2008
    Assignee: LSI Logic Corporation
    Inventors: Chok J. Chia, Allen Seng Sooi Lim, Maurice O. Othieno
  • Patent number: 7235889
    Abstract: The present invention is directed toward systems, packages, and methods for providing improved thermal performance in such packages and systems. Embodiments of the invention include a semiconductor integrated circuit (IC) package having a substrate with a heat spreader mounted on the substrate. An IC die is mounted to the heat spreader such that the heat spreader lies in between the die and the substrate. The invention is also directed to a heat spreader plate useable in a semiconductor package. The heat spreader plate comprises a plate comprised of thermally conductive material suitable for attachment to a packaging substrate wherein the plate includes openings for exposing electrical bonding surfaces of a packaging substrate when the heater spreader plate is mounted on the packaging substrate. Such openings enable wirebonding between the exposed electrical bonding surfaces of the substrate and an integrated circuit die to complete construction of a package including the heatspreader.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: June 26, 2007
    Assignee: LSI Corporation
    Inventors: Maurice O. Othieno, Hong T. Lim, Qwai H. Low
  • Patent number: 6867480
    Abstract: A method of shielding an integrated circuit from electromagnetic interference. The integrated circuit is at least partially encapsulated within an electromagnetic interference resistant molding compound, and then the integrated circuit is completely encapsulated within a second molding compound. In this manner, the electromagnetic interference resistant molding compound protects the integrated circuit from electromagnetic interference, while the second molding compound can be selected for properties traditionally desired in a molding compound, such as thermal, electrical insulating, and structural properties. Thus, the integrated circuit according to the present invention can be placed closer to structures, such as power supplies, which produce electromagnetic interference, without experiencing an unacceptable degradation of performance due to the electromagnetic interference caused by the structures.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: March 15, 2005
    Assignee: LSI Logic Corporation
    Inventors: Severino A. Legaspi, Jr., Manickam Thavarajah, Maurice O. Othieno, Pradip D. Patel
  • Publication number: 20040251522
    Abstract: A method of shielding an integrated circuit from electromagnetic interference. The integrated circuit is at least partially encapsulated within an electromagnetic interference resistant molding compound, and then the integrated circuit is completely encapsulated within a second molding compound. In this manner, the electromagnetic interference resistant molding compound protects the integrated circuit from electromagnetic interference, while the second molding compound can be selected for properties traditionally desired in a molding compound, such as thermal, electrical insulating, and structural properties. Thus, the integrated circuit according to the present invention can be placed closer to structures, such as power supplies, which produce electromagnetic interference, without experiencing an unacceptable degradation of performance due to the electromagnetic interference caused by the structures.
    Type: Application
    Filed: June 10, 2003
    Publication date: December 16, 2004
    Inventors: Severino A. Legaspi, Manickam Thavarajah, Maurice O. Othieno, Pradip D. Patel
  • Patent number: 6801437
    Abstract: A method of forming electrically conductive elements on a base layer of an electronic substrate without the use of solder mask. A layer of electrically conductive material is deposited on the base layer, and a first layer of photo imageable ink is applied over the electrically conductive material layer. The first layer of photo imageable ink is patterned to expose portions of the electrically conductive material layer, which are then etched to resolve traces in the electrically conductive material layer. The first layer of photo imageable ink is removed, and a second layer of photo imageable ink is applied over the traces and channels between the traces. The second layer of photo imageable ink is then patterned to expose the traces, and a third layer of photo imageable ink is applied over the traces and the second layer of photo imageable ink. The third layer of photo imageable ink is patterned to expose deposition sites on the traces, within which are formed electrically conductive fingers.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: October 5, 2004
    Assignee: LSI Logic Corporation
    Inventors: Maurice O. Othieno, Manickam Thavarajah, Severino A. Legaspi, Jr., Pradip D. Patel
  • Publication number: 20040142556
    Abstract: A method of forming electrically conductive elements on a base layer of an electronic substrate without the use of solder mask. A layer of electrically conductive material is deposited on the base layer, and a first layer of photo imageable ink is applied over the electrically conductive material layer. The first layer of photo imageable ink is patterned to expose portions of the electrically conductive material layer, which are then etched to resolve traces in the electrically conductive material layer. The first layer of photo imageable ink is removed, and a second layer of photo imageable ink is applied over the traces and channels between the traces. The second layer of photo imageable ink is then patterned to expose the traces, and a third layer of photo imageable ink is applied over the traces and the second layer of photo imageable ink. The third layer of photo imageable ink is patterned to expose deposition sites on the traces, within which are formed electrically conductive fingers.
    Type: Application
    Filed: January 21, 2003
    Publication date: July 22, 2004
    Inventors: Maurice O. Othieno, Manickam Thavarajah, Severino A. Legaspi, Pradip D. Patel
  • Patent number: 6654248
    Abstract: A heat spreader for use with an integrated circuit in a package, where the heat spreader is formed as a plate having a centrally disposed aperture with a diameter that is smaller than a minimum diameter of the integrated circuit. The heat spreader has an overall diameter that is no greater than a minimum diameter of the package. In this manner, the aperture in the heat spreader allows the plastic injected through a top gated mold form to pass through the heat spreader and more uniformly encapsulate the integrated circuit.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: November 25, 2003
    Assignee: LSI Logic Corporation
    Inventors: Clifford R. Fishley, Maurice O. Othieno
  • Patent number: 6603201
    Abstract: A package substrate having sides, which is formed of multiple non electrically conductive layers laminated together. Each of the multiple non electrically conductive layers is formed of a first lamina and a second lamina bonded together in a resin matrix. The first lamina is formed of woven fibers having a first warp. The first warp of the first lamina is disposed at a positive orientation of a first angle from the sides of the package substrate, where the first angle is neither zero degrees nor ninety degrees. The second lamina is also formed of woven fibers, having a second warp. The second warp of the second lamina is disposed at a negative orientation of the first angle from the sides of the package substrate. Electrically conductive layers are dispersed between different ones of the multiple non electrically conductive layers, with electrical connections dispersed between different ones of the electrically conductive layers.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: August 5, 2003
    Assignee: LSI Logic Corporation
    Inventors: Manickam Thavarajah, Maurice O. Othieno, Severino A. Legaspi, Jr., Pradip D. Patel