Patents by Inventor Maurice S. Karpman

Maurice S. Karpman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10681821
    Abstract: Techniques for constructing a wafer based module are provided herein. For example, the techniques include providing a substrate, forming a pattern of conductive material relative to at least one of a surface plane of the substrate and an internal location within the substrate with the pattern of the conductive material including at least an exposed portion, mounting at least one electronic module to the exposed portion of the pattern of the conductive material, orienting the substrate orthogonal relative to a planar mounting surface such that the surface plane of the substrate is substantially orthogonal to the planar mounting surface, mounting one or more additional electronic modules on the planar mounting surface; and forming the semiconductor device by encapsulating the substrate, including the pattern of conductive material, the at least one electronic module and the one or more additional electronic modules within a mold compound.
    Type: Grant
    Filed: October 16, 2014
    Date of Patent: June 9, 2020
    Assignee: THE CHARLES STARK DRAPER LABORATORY, INC.
    Inventor: Maurice S. Karpman
  • Patent number: 10453787
    Abstract: An electronic module assembly including a via spanning multiple layers in a wafer based module is described. The electronic module assembly can include a first layer deposited upon a substrate, a second layer deposited on a top surface of the first layer, and the via spanning multiple layers. The via can include a first bottom that is formed on a top surface of the first layer and a first sidewall that upstands from the first bottom and extending at least through the second layer.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: October 22, 2019
    Assignee: THE CHARLES STARK DRAPER LABORATORY, INC.
    Inventors: Maurice S. Karpman, Nicole S. Mueller, Gary B. Tepolt, Russell Berman
  • Patent number: 10315914
    Abstract: A one or multi-die module comprises multiple dies. The module includes at least one die with a sensor having a sensing region, an encapsulation layer covering top sides of the multiple dies, and a redistribution layer (RDL) covering bottom sides of the multiple dies except for the sensing region. In embodiments, a cap is formed over the sensing region, which has at least a portion that is spaced away from a bottom side of the module. Metal connectors, such as solder balls, are formed on the redistribution layer to provide connection points to the module. This approach can be used to incorporate environmental sensor dies into multi-die modules. It utilizes RDL and openings in the RDL in order to provide robust packaging for the dies, while also allowing the sensor dies to be selectively exposed to the environment.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: June 11, 2019
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventor: Maurice S. Karpman
  • Patent number: 10265516
    Abstract: The present disclosure describes a closely spaced array of penetrating electrodes. In some implementations, the electrodes of the array are spaced less than 50 ?m apart. The present disclosure also describes methods for manufacturing the closely spaced array of penetrating electrodes. In some implementations, each row of electrode of the array is manufactured in-plane and then coupled to other rows of electrodes to form an array.
    Type: Grant
    Filed: November 21, 2016
    Date of Patent: April 23, 2019
    Assignee: The Charles Stark Draper Laboratory, Inc.
    Inventors: Maurice S. Karpman, Andrew Meuller
  • Patent number: 9941223
    Abstract: Techniques for providing a tamper mechanism for semiconductor devices are disclosed herein. The techniques include, for example, providing at least one die and at least one strain gauge, orienting the at least one strain gauge to the die, forming an encapsulated semiconductor device by encapsulating the die and each strain gauge within a mold compound to maintain respective orientation, and measuring an initial strain value for the at least one strain gauge after forming the encapsulated semiconductor device.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: April 10, 2018
    Assignee: THE CHARLES STARK DRAPER LABORATORY, INC.
    Inventor: Maurice S. Karpman
  • Publication number: 20170369307
    Abstract: A one or multi-die module comprises multiple dies. The module includes at least one die with a sensor having a sensing region, an encapsulation layer covering top sides of the multiple dies, and a redistribution layer covering bottom sides of the multiple dies except for the sensing region. In embodiments, a cap is formed over the sensing region, which has at least a portion that is spaced away from a bottom side of the module. Metal connectors, such as solder balls, are formed on the redistribution layer to provide connection points to the module. A height of the cap from the bottom side of the module should be less than a height of the metal connectors. This approach can be used to incorporate environmental sensor dies into multi-die modules. It utilizes RDL and openings in the RDL in order to provide robust packaging for the dies, while also allowing the sensor dies to be selectively exposed to the environment.
    Type: Application
    Filed: June 27, 2017
    Publication date: December 28, 2017
    Inventor: Maurice S. Karpman
  • Publication number: 20170165474
    Abstract: The present disclosure describes a closely spaced array of penetrating electrodes. In some implementations, the electrodes of the array are spaced less than 50 ?m apart. The present disclosure also describes methods for manufacturing the closely spaced array of penetrating electrodes. In some implementations, each row of electrode of the array is manufactured in-plane and then coupled to other rows of electrodes to form an array.
    Type: Application
    Filed: November 21, 2016
    Publication date: June 15, 2017
    Inventors: Maurice S. Karpman, Andrew Meuller
  • Publication number: 20160343652
    Abstract: An electronic module assembly including a via spanning multiple layers in a wafer based module is described. The electronic module assembly can include a first layer deposited upon a substrate, a second layer deposited on a top surface of the first layer, and the via spanning multiple layers. The via can include a first bottom that is formed on a top surface of the first layer and a first sidewall that upstands from the first bottom and extending at least through the second layer.
    Type: Application
    Filed: May 20, 2016
    Publication date: November 24, 2016
    Inventors: Maurice S. Karpman, Nicole S. Mueller, Gary B. Tepolt, Russell Berman
  • Publication number: 20160113139
    Abstract: Techniques for constructing a wafer based module are provided herein. For example, the techniques include providing a substrate, forming a pattern of conductive material relative to at least one of a surface plane of the substrate and an internal location within the substrate with the pattern of the conductive material including at least an exposed portion, mounting at least one electronic module to the exposed portion of the pattern of the conductive material, orienting the substrate orthogonal relative to a planar mounting surface such that the surface plane of the substrate is substantially orthogonal to the planar mounting surface, mounting one or more additional electronic modules on the planar mounting surface; and forming the semiconductor device by encapsulating the substrate, including the pattern of conductive material, the at least one electronic module and the one or more additional electronic modules within a mold compound.
    Type: Application
    Filed: October 16, 2014
    Publication date: April 21, 2016
    Inventor: Maurice S. Karpman
  • Publication number: 20160043043
    Abstract: Techniques for providing a tamper mechanism for semiconductor devices are disclosed herein. The techniques include, for example, providing at least one die and at least one strain gauge, orienting the at least one strain gauge to the die, forming an encapsulated semiconductor device by encapsulating the die and each strain gauge within a mold compound to maintain respective orientation, and measuring an initial strain value for the at least one strain gauge after forming the encapsulated semiconductor device.
    Type: Application
    Filed: August 7, 2015
    Publication date: February 11, 2016
    Applicant: The Charles Stark Draper Laboratory, Inc.
    Inventor: Maurice S. Karpman
  • Patent number: 7608534
    Abstract: Bridge structures provide a surface on which to form interconnections to components through through-hole vias. The bridge structures at least partially, and preferably fully, span the gap between two wafers, and, more specifically, between a through-hole via in one wafer and a corresponding component on the other wafer. Bridge structure may be formed on the wafer having the through-hole via and/or the wafer having the component.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: October 27, 2009
    Assignee: Analog Devices, Inc.
    Inventors: Changhan Yun, Javier Villarreal, Maurice S. Karpman
  • Publication number: 20080225505
    Abstract: A method of producing a MEMS device removes the bottom side of a device wafer after its movable structure is formed. To that end, the method provides the device wafer, which has an initial bottom side. Next, the method forms the movable structure on the device wafer, and then removes substantially the entire initial bottom side of the device wafer. Removal of the entire initial bottom side effectively forms a final bottom side.
    Type: Application
    Filed: May 29, 2008
    Publication date: September 18, 2008
    Applicant: ANALOG DEVICES, INC.
    Inventors: John R. Martin, Manolo G. Mena, Elmer S. Lacsamana, Michael P. Duffy, William A. Webster, Lawrence E. Felton, Maurice S. Karpman
  • Patent number: 7416984
    Abstract: A method of producing a MEMS device removes the bottom side of a device wafer after its movable structure is formed. To that end, the method provides the device wafer, which has an initial bottom side. Next, the method forms the movable structure on the device wafer, and then removes substantially the entire initial bottom side of the device wafer. Removal of the entire initial bottom side effectively forms a final bottom side.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: August 26, 2008
    Assignee: Analog Devices, Inc.
    Inventors: John R. Martin, Manolo G. Mena, Elmer S. Lacsamana, Maurice S. Karpman
  • Patent number: 7166911
    Abstract: A MEMS inertial sensor is secured within a premolded-type package formed, at least in part, from a low moisture permeable molding material. Consequently, such a motion detector should be capable of being produced more economically than those using ceramic packages. To those ends, the package has at least one wall (having a low moisture permeability) extending from a leadframe to form a cavity, and an isolator (with a top surface) within the cavity. The MEMS inertial sensor has a movable structure suspended above a substrate having a bottom surface. The substrate bottom surface is secured to the isolator top surface at a contact area. In illustrative embodiments, the contact area is less than the surface area of the bottom surface of the substrate. Accordingly, the isolator forms a space between at least a portion of the bottom substrate surface and the package. This space thus is free of the isolator.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: January 23, 2007
    Assignee: Analog Devices, Inc.
    Inventors: Maurice S. Karpman, Nicole Hablutzel, Peter W. Farrell, Michael W. Judy, Lawrence E. Felton, Lewis Long
  • Patent number: 6964882
    Abstract: A flip-bonding technique is used to fabricate complex micro-electromechanical systems. Various micromachined structures are fabricated on the front side of each of two wafers. One of the wafers is flipped over and bonded to the other wafer so that the front sides of the two wafers are bonded together in a flip-stacked configuration.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: November 15, 2005
    Assignee: Analog Devices, Inc.
    Inventors: Chang-Han Yun, Lawrence E. Felton, Maurice S. Karpman, John A. Yasaitis, Michael W. Judy, Colin Gormley
  • Patent number: 6946742
    Abstract: A packaged microchip has a stress sensitive microchip, a package having a package modulus of elasticity, and an isolator between the microchip and the package. The isolator has an isolator modulus of elasticity that has a relationship with the package modulus of elasticity. This relationship causes no more than a negligible thermal stress to be transmitted to the microchip.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: September 20, 2005
    Assignee: Analog Devices, Inc.
    Inventor: Maurice S. Karpman
  • Patent number: 6933163
    Abstract: An intermediate electrode layer is used to fabricate an integrated micro-electromechanical system. An intermediate electrode layer is formed on an integrated circuit wafer. The intermediate electrode layer places drive electrodes a predetermined height above the surface of the integrated circuit wafer. A micro-electromechanical system wafer having micromachined optical mirrors is bonded to the integrated circuit wafer such that the drive electrodes are positioned a predetermined distance from the optical mirrors.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: August 23, 2005
    Assignee: Analog Devices, Inc.
    Inventors: Chang-Han Yun, Lawrence E. Felton, Maurice S. Karpman, John A. Yasaitis, Michael W. Judy, Colin Gormley
  • Patent number: 6893976
    Abstract: A method of producing a shadow mask having a set of apertures (the set of apertures including a given aperture with an aperture boundary) uses a wafer having at least a first silicon layer, a second silicon layer, and an insulator layer between the first and second silicon layers. A first portion of the first silicon layer within the aperture boundary is removed. This produces a second portion of the first silicon layer, which remains within the aperture boundary. The second silicon layer within the aperture boundary is removed, as well as the insulator layer within the aperture boundary. The second portion of the first silicon layer remaining within the aperture boundary then is removed.
    Type: Grant
    Filed: September 5, 2002
    Date of Patent: May 17, 2005
    Assignee: Analog Devices, Inc.
    Inventors: Maurice S. Karpman, Swaminathan Rajaraman
  • Publication number: 20040119143
    Abstract: A packaged microchip has a stress sensitive microchip, a package having a package modulus of elasticity, and an isolator between the microchip and the package. The isolator has an isolator modulus of elasticity that has a relationship with the package modulus of elasticity. This relationship causes no more than a negligible thermal stress to be transmitted to the microchip.
    Type: Application
    Filed: December 19, 2002
    Publication date: June 24, 2004
    Inventor: Maurice S. Karpman
  • Publication number: 20040063239
    Abstract: An intermediate electrode layer is used to fabricate an integrated micro-electromechanical system. An intermediate electrode layer is formed on an integrated circuit wafer. The intermediate electrode layer places drive electrodes a predetermined height above the surface of the integrated circuit wafer. A micro-electromechanical system wafer having micromachined optical mirrors is bonded to the integrated circuit wafer such that the drive electrodes are positioned a predetermined distance from the optical mirrors.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 1, 2004
    Inventors: Chang-Han Yun, Lawrence E. Felton, Maurice S. Karpman, John A. Yasaitis, Michael W. Judy, Colin Gormley