Abstract: A TDD signal booster includes first and second bidirectional terminals and an amplifier circuit arranged in a signal path between said first and second terminals. The amplifier circuit is to amplify TDD signals received at one of said first and second terminals for transmission from the other of said first and second terminals. The amplifier circuit is operable in a first configuration for amplifying TDD signals in one direction along the signal path and a second configuration for amplifying TDD signals in the opposite direction along the signal path. A control circuit is arranged to detect a silent period in said TDD signals, e.g. the guard period, and, in response to detecting the silent period, control said amplifier circuit to change configuration.

Abstract: A TDD signal booster includes first and second bidirectional terminals and an amplifier circuit arranged in a signal path between said first and second terminals. The amplifier circuit is to amplify TDD signals received at one of said first and second terminals for transmission from the other of said first and second terminals. The amplifier circuit is operable in a first configuration for amplifying TDD signals in one direction along the signal path and a second configuration for amplifying TDD signals in the opposite direction along the signal path. A control circuit is arranged to detect a silent period in said TDD signals, e.g. the guard period, and, in response to detecting the silent period, control said amplifier circuit to change configuration.

Abstract: A device for managing signal transport, on a cable level, in a communication system, and a method for using same, are provided herein. The device is connectable between one or more access multiplexers (e.g., Very-high-speed Digital Subscriber Loop Access Multiplexer (VDSLAM) or a switch) and a cable in said communication system. The device includes: a plurality of access multiplexer-side transceivers connectable to access multiplexer-related physical medium, associated with said one or more access multiplexers; a plurality of customer-side transceivers connectable to respective customer-related wire pairs of said cable; and a processor connected to said access multiplexer-side transceivers and said customer-side transceivers, said processor comprising means for reducing crosstalk among said customer-related wire pairs. In some embodiments, vectoring is used for the crosstalk reduction, thus implementing a so-called cable level vectoring (CLV).

Abstract: A device for managing signal transport, on a cable level, in a communication system, and a method for using same, are provided herein. The device is connectable between one or more access multiplexers (e.g., Very-high-speed Digital Subscriber Loop Access Multiplexer (VDSLAM) or a switch) and a cable in said communication system. The device includes: a plurality of access multiplexer-side transceivers connectable to access multiplexer-related physical medium, associated with said one or more access multiplexers; a plurality of customer-side transceivers connectable to respective customer-related wire pairs of said cable; and a processor connected to said access multiplexer-side transceivers and said customer-side transceivers, said processor comprising means for reducing crosstalk among said customer-related wire pairs. In some embodiments, vectoring is used for the crosstalk reduction, thus implementing a so-called cable level vectoring (CLV).

Abstract: A system and method for transmitting and recovering external clock signals over links of a DSL system in which the external clock signals are used to synchronize transmitted physical layer signals from a CO of a DSL system and said external clock signals are derived from the received physical layer signals at an RT/CPE location of a DSL system. A clock recovery subsystem located at both the CO and the RT/CPE comprises a clock monitor circuit in communication with a Phase Lock Loop circuit. The clock monitor circuit at the RT/CPE is able to derive clock signals from the received physical layer signals and select one of said derived clocks to which a local reference clock at the RT/CPE is synchronized. The synchronized local reference clock, which can exist even when there are no valid derived clocks, may be used to transmit pseudowire frames (e.g., TDM data over Ethernet).

Abstract: A system and method for transmitting and recovering external clock signals over links of a DSL system in which the external clock signals are used to synchronize transmitted physical layer signals from a CO of a DSL system and said external clock signals are derived from the received physical layer signals at an RT/CPE location of a DSL system. A clock recovery sub-system located at both the CO and the RT/CPE comprises a clock monitor circuit in communication with a Phase Lock Loop circuit. The clock monitor circuit at the RT/CPE is able to derive clock signals from the received physical layer signals and select one of said derived clocks to which a local reference clock at the RT/CPE is synchronized. The synchronized local reference clock, which can exist even when there are no valid derived clocks, may be used to transmit pseudowire frames (e.g., TDM data over Ethernet).