Abstract: Integrated circuit structures having differentiated source or drain structures are described. In an example, an integrated circuit structure includes first, second and third pluralities of horizontally stacked nanowires or fins, and first, second and third gate stacks. A first epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the first epitaxial source or drain structure having a lateral width and a composition. A second epitaxial source or drain structure is between the second plurality of horizontally stacked nanowires or fin and the third plurality of horizontally stacked nanowires or fin, the second epitaxial source or drain structure having the composition of the first epitaxial source or drain structure, and the second epitaxial source or drain structure having a lateral width less than the lateral width of the first epitaxial source or drain structure.

Abstract: Gate-all-around integrated circuit structures having asymmetric source and drain contact structures, and methods of fabricating gate-all-around integrated circuit structures having asymmetric source and drain contact structures, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires above a fin. A gate stack is over the vertical arrangement of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. A first conductive contact structure is coupled to the first epitaxial source or drain structure. A second conductive contact structure is coupled to the second epitaxial source or drain structure. The second conductive contact structure is deeper along the fin than the first conductive contact structure.

Abstract: Integrated circuit structures having partitioned source or drain contact structures, and methods of fabricating integrated circuit structures having partitioned source or drain contact structures, are described. For example, an integrated circuit structure includes a fin. A gate stack is over the fin. A first epitaxial source or drain structure is at a first end of the fin. A second epitaxial source or drain structure is at a second end of the fin. A conductive contact structure is coupled to one of the first or the second epitaxial source or drain structures. The conductive contact structure has a first portion partitioned from a second portion.

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing for integrating photonic and electronic components, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by bonding at least two IC structures fabricated using different manufacturers, materials, or manufacturing techniques. Before bonding, at least one IC structure may include photonic components such as optical waveguides, electro-optic modulators, and monolithically integrated lenses, and at least one may include electronic components such as electrically conductive interconnects, transistors, and resistors. One or more additional electronic and/or photonic components may be provided in one or more of these IC structures after bonding. For example, an interconnect implemented as an electrically conductive via or a waveguide implemented as a dielectric via may be provided after bonding to extend through one or more of the bonded IC structures.

Abstract: Methods for fabricating a transistor arrangement of an IC structure by using a placeholder for backside contact formation, as well as related semiconductor devices, are disclosed. An example method includes forming, in a support structure (e.g., a substrate, a chip, or a wafer), a dielectric placeholder for a backside contact as the first step in the method. A nanosheet superlattice is then grown laterally over the dielectric placeholder, and a stack of nanoribbons is formed based on the superlattice. The nanoribbons are processed to form S/D regions and gate stacks for future transistors. The dielectric placeholder remains in place until the support structure is transferred to a carrier wafer, at which point the dielectric placeholder is replaced with the backside contact. Use of a placeholder for backside contact formation allows alignment of contact from the backside to appropriate device ports of a transistor arrangement.

Abstract: Structures having alternative carriers for dual-sided devices are described. In an example, an integrated circuit structure includes a front side structure including a device layer, and a plurality of metallization layers above the device layer. A backside structure is below the device layer. A carrier wafer or substrate is bonded directly to and is in contact with the front side structure, or is bonded to the front side structure by a compliant bonding layer.

Abstract: Integrated circuit structures having backside source or drain contact selectivity are described. In an example, an integrated circuit structure includes a first epitaxial source or drain structure at an end of a first plurality of horizontally stacked nanowires or fin, with a first conductive source or drain contact vertically beneath and in contact with a bottom of the first epitaxial source or drain structure, and with a first hardmask material beneath and in contact with the first conductive source or drain contact. A second epitaxial source or drain structure is at an end of a second plurality of horizontally stacked nanowires or fin, with a second conductive source or drain contact vertically beneath and in contact with a bottom of the second epitaxial source or drain structure, and a second hardmask material beneath and in contact with the second conductive source or drain contact.

Abstract: Integrated circuit structures having backside contact reveal uniformity, and methods of fabricating integrated circuit structures having backside contact reveal uniformity, are described. In an example, an integrated circuit structure includes an integrated circuit structure including a plurality of horizontally stacked nanowires or a fin. A gate stack is over the plurality of horizontally stacked nanowires or the fin. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires or the fin. A conductive source or drain contact is vertically beneath and in contact with a bottom of the epitaxial source or drain structure. The conductive source or drain contact is in a cavity in the isolation layer. The isolation layer extends laterally beneath the gate stack.

Abstract: Guard rings are described. In an example, a semiconductor die includes an active device layer including a plurality of nanoribbon devices. A dielectric structure is over the active device layer. A first die-edge metal guard ring is in the dielectric structure and around an outer perimeter of the plurality of nanoribbon devices. A plurality of metallization layers is in the dielectric structure and within the first die-edge metal guard ring. A plurality of direct backside contacts extend to the active device layer. A plurality of backside metallization structures is beneath the plurality of direct backside contacts. The plurality of direct backside contacts are connected to the plurality of backside metallization structures. A second die-edge metal guard ring is laterally around the plurality of backside metallization structures.

Abstract: Various aspects of the present disclosure set forth IC dies, microelectronic assemblies, as well as related devices and packages, related to direct chip attach of dies and circuit boards. An example microelectronic assembly includes a die with IC components provided over the die's frontside, and a metallization stack provided over the die's backside. The die further includes die interconnects extending between the frontside and the backside of the die, to electrically couple the IC components and the metallization stack. The assembly further includes backside conductive contacts, provided over the side of the metallization stack facing away from the die, the backside conductive contacts configured to route signals to/from the IC components via the metallization stack and the die interconnects, and configured to be coupled to respective conductive contacts of a circuit board in absence of a package substrate between the die and the circuit board.

Abstract: Integrated circuit structures having backside contact stitching are described. In an example, an integrated circuit structure includes a first plurality of horizontally stacked nanowires laterally spaced apart from a second plurality of horizontally stacked nanowires. First and second epitaxial source or drain structure are at respective ends of the first and second pluralities of horizontally stacked nanowires. A conductive contact structure is beneath and in contact with the first epitaxial source or drain structure and the second epitaxial source or drain structure, and the conductive contact structure is continuous between the first and second epitaxial source or drain structures. The conductive contact structure has a first vertical thickness beneath the first and second epitaxial source or drain structures greater than a second vertical thickness in a region between the first and second epitaxial source or drain structures.

Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

Abstract: Methods for fabricating a transistor arrangement of an IC structure by using a placeholder for backside contact formation, as well as related semiconductor devices, are disclosed. An example method includes forming, in a support structure (e.g., a substrate, a chip, or a wafer), a dielectric placeholder for a backside contact as the first step in the method. A nanosheet superlattice is then grown laterally over the dielectric placeholder, and a stack of nanoribbons is formed based on the superlattice. The nanoribbons are processed to form S/D regions and gate stacks for future transistors. The dielectric placeholder remains in place until the support structure is transferred to a carrier wafer, at which point the dielectric placeholder is replaced with the backside contact. Use of a placeholder for backside contact formation allows alignment of contact from the backside to appropriate device ports of a transistor arrangement.

Abstract: Microelectronic assemblies fabricated using hybrid manufacturing for integrating photonic and electronic components, as well as related devices and methods, are disclosed herein. As used herein, “hybrid manufacturing” refers to fabricating a microelectronic assembly by bonding at least two IC structures fabricated using different manufacturers, materials, or manufacturing techniques. Before bonding, at least one IC structure may include photonic components such as optical waveguides, electro-optic modulators, and monolithically integrated lenses, and at least one may include electronic components such as electrically conductive interconnects, transistors, and resistors. One or more additional electronic and/or photonic components may be provided in one or more of these IC structures after bonding. For example, an interconnect implemented as an electrically conductive via or a waveguide implemented as a dielectric via may be provided after bonding to extend through one or more of the bonded IC structures.

Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming a package that has a transistor layer with a front side metal interconnect layer and a back side metal contact and interconnect layer. In particular, back side metal contact and interconnect layers may be patterned before a transistor layer, or other device layer, is formed on the patterned layers and before front side metal interconnect layers are formed on the transistor layer. Other embodiments may be described and/or claimed.

Abstract: Embodiments described herein may be related to apparatuses, processes, systems, and/or techniques for forming backside contacts on a transistor structure by forming, during front-side processing, trenches through the transistor structure into a silicon wafer, and then, using a catalytic oxidant material that is subsequently removed, forming an oxide structure in the silicon wafer around the trenches to isolate the backside gate contact from the source/drain trenches. Other embodiments may be described and/or claimed.

Abstract: Integrated circuit structures having backside source or drain contact selectivity are described. In an example, an integrated circuit structure includes a first epitaxial source or drain structure at an end of a first plurality of horizontally stacked nanowires or fin, with a first conductive source or drain contact vertically beneath and in contact with a bottom of the first epitaxial source or drain structure, and with a first hardmask material beneath and in contact with the first conductive source or drain contact. A second epitaxial source or drain structure is at an end of a second plurality of horizontally stacked nanowires or fin, with a second conductive source or drain contact vertically beneath and in contact with a bottom of the second epitaxial source or drain structure, and a second hardmask material beneath and in contact with the second conductive source or drain contact.

Abstract: Integrated circuit structures having backside gate connection are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires or a fin. A gate stack is over the plurality of horizontally stacked nanowires or the fin. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires or the fin. A conductive gate-to-contact connection is vertically beneath the epitaxial source or drain structure and vertically beneath and in electrical contact with the gate stack.

Abstract: Integrated circuit structures having backside contact widening are described. In an example, an integrated circuit structure includes a plurality of horizontally stacked nanowires. A gate stack is over the plurality of horizontally stacked nanowires. An epitaxial source or drain structure is at an end of the plurality of horizontally stacked nanowires. A conductive gate contact is vertically beneath and in contact with a bottom of the gate stack. The conductive gate contact is in a cavity in an isolation layer, the cavity extending beyond the gate stack in a direction parallel with the epitaxial source or drain structure, and the cavity confined to the gate stack in a direction toward the epitaxial source or drain structure.