Patents by Inventor Mauro J. Kobrinsky

Mauro J. Kobrinsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210335791
    Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.
    Type: Application
    Filed: July 6, 2021
    Publication date: October 28, 2021
    Applicant: Intel Corporation
    Inventors: Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa, Elliot Tan, Tahir Ghani, Swaminathan Sivakumar
  • Patent number: 11139300
    Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa, Elliot Tan, Tahir Ghani, Swaminathan Sivakumar
  • Patent number: 11139241
    Abstract: Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: October 5, 2021
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Mauro J. Kobrinsky, Mark T. Bohr, Tahir Ghani, Rishabh Mehandru, Ranjith Kumar
  • Publication number: 20210272624
    Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density 3D SRAM. An example device includes an SRAM cell built based on a first nanoribbon, suitable for forming NMOS transistors, and a second nanoribbon, suitable for forming PMOS transistors. Both nanoribbons may extend substantially in the same plane above a support structure over which the memory device is provided. The SRAM cell includes transistors M1-M4, arranged to form two inverter structures. The first inverter structure includes transistor M1 in the first nanoribbon and transistor M2 in the second nanoribbon, while the second inverter structure includes transistor M3 in the first nanoribbon and transistor M4 in the second nanoribbon. The IC device may include multiple layers of nanoribbons, with one or more such SRAM cells in each layer, stacked upon one another above the support structure, thus realizing 3D SRAM.
    Type: Application
    Filed: March 2, 2020
    Publication date: September 2, 2021
    Applicant: Intel Corporation
    Inventors: Wilfred Gomes, Kinyip Phoa, Mauro J. Kobrinsky, Tahir Ghani
  • Patent number: 11087832
    Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density 3D SRAM. An example device includes an SRAM cell built based on a first nanoribbon, suitable for forming NMOS transistors, and a second nanoribbon, suitable for forming PMOS transistors. Both nanoribbons may extend substantially in the same plane above a support structure over which the memory device is provided. The SRAM cell includes transistors M1-M4, arranged to form two inverter structures. The first inverter structure includes transistor M1 in the first nanoribbon and transistor M2 in the second nanoribbon, while the second inverter structure includes transistor M3 in the first nanoribbon and transistor M4 in the second nanoribbon. The IC device may include multiple layers of nanoribbons, with one or more such SRAM cells in each layer, stacked upon one another above the support structure, thus realizing 3D SRAM.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 10, 2021
    Assignee: Intel Corporation
    Inventors: Wilfred Gomes, Kinyip Phoa, Mauro J. Kobrinsky, Tahir Ghani
  • Patent number: 11062995
    Abstract: An integrated circuit includes a base with one or more semiconductor devices. An insulating material is over the base and an interconnect structure is over the base. The interconnect structure includes vertical conductors extending through the insulating material in a spaced-apart arrangement. The interconnect structure comprises a conductor and a chalcogen, the chalcogen present in an amount of up to 5 atomic percent. In some embodiments, the chalcogen is present in an amount less than 2 atomic percent or less than 1 atomic percent.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: July 13, 2021
    Assignee: Intel Corporation
    Inventors: Carl H. Naylor, Mauro J. Kobrinsky
  • Patent number: 11056492
    Abstract: Described herein are memory arrays where some memory cells include access transistors with one front-side and one back-side source/drain (S/D) contacts. An example memory array further includes a bitline, coupled to the first S/D region of the access transistor of a first memory cell of the memory array, and a plateline, coupled to a first capacitor electrode of a storage capacitor of the first memory cell. Because the access transistor is a transistor with one front-side and one back-side S/D contacts, the bitline may be provided in a first layer, the channel material—in a second layer, and the plateline—in a third layer, where the second layer is between the first layer and the third layer, which may allow increasing the density of memory cells in a memory array, or, conversely, reducing the footprint area of a memory array with a given density of memory cells.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Wilfred Gomes, Mauro J. Kobrinsky, Elliot Tan, Szuya S. Liao, Tahir Ghani, Swaminathan Sivakumar, Rajesh Kumar
  • Patent number: 11056356
    Abstract: Techniques and mechanisms for bonding a first wafer to a second wafer in the presence of a fluid, the viscosity of which is greater than a viscosity of air at standard ambient temperature and pressure. In an embodiment, a first surface of the first wafer is brought into close proximity to a second surface of the second wafer. The fluid is provided between the first surface and the second surface when a first region of the first surface is made to contact a second region of the second surface to form a bond. The viscosity of the fluid mitigates a rate of propagation of the bond along a wafer surface, which in turn mitigates wafer deformation and/or stress between wafers. In another embodiment, the viscosity of the fluid is changed dynamically while the bond propagates between the first surface and the second surface.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Brennen K. Mueller, Daniel Pantuso, Mauro J. Kobrinsky, Chytra Pawashe, Myra McDonnell
  • Publication number: 20210193666
    Abstract: Described herein are memory arrays where some memory cells include access transistors with one front-side and one back-side source/drain (S/D) contacts. An example memory array further includes a bitline, coupled to the first S/D region of the access transistor of a first memory cell of the memory array, and a plateline, coupled to a first capacitor electrode of a storage capacitor of the first memory cell. Because the access transistor is a transistor with one front-side and one back-side S/D contacts, the bitline may be provided in a first layer, the channel material—in a second layer, and the plateline—in a third layer, where the second layer is between the first layer and the third layer, which may allow increasing the density of memory cells in a memory array, or, conversely, reducing the footprint area of a memory array with a given density of memory cells.
    Type: Application
    Filed: December 23, 2019
    Publication date: June 24, 2021
    Applicant: Intel Corporation
    Inventors: Wilfred Gomes, Mauro J. Kobrinsky, Elliot Tan, Szuya S. Liao, Tahir Ghani, Swaminathan Sivakumar, Rajesh Kumar
  • Publication number: 20210159229
    Abstract: Described herein are IC devices that include semiconductor nanoribbons stacked over one another to realize high-density three-dimensional (3D) dynamic random-access memory (DRAM). An example device includes a first semiconductor nanoribbon, a second semiconductor nanoribbon, a first source or drain (S/D) region and a second S/D region in each of the first and second nanoribbons, a first gate stack at least partially surrounding a portion of the first nanoribbon between the first and second S/D regions in the first nanoribbon, and a second gate stack, not electrically coupled to the first gate stack, at least partially surrounding a portion of the second nanoribbon between the first and second S/D regions in the second nanoribbon. The device further includes a bitline coupled to the first S/D regions of both the first and second nanoribbons.
    Type: Application
    Filed: November 21, 2019
    Publication date: May 27, 2021
    Applicant: Intel Corporation
    Inventors: Wilfred Gomes, Kinyip Phoa, Mauro J. Kobrinsky, Tahir Ghani, Uygar E. Avci, Rajesh Kumar
  • Publication number: 20210151438
    Abstract: A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.
    Type: Application
    Filed: November 20, 2019
    Publication date: May 20, 2021
    Applicant: Intel Corporation
    Inventors: Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Rajesh Kumar, Kinyip Phoa, Elliot Tan, Tahir Ghani, Swaminathan Sivakumar
  • Publication number: 20210134802
    Abstract: Described herein are IC devices that include transistors with contacts to one of the source/drain (S/D) regions being on the front side of the transistors and contacts to the other one of the S/D regions being on the back side of the transistors (i.e., “back-side contacts”). Using transistors with one front-side and one back-side S/D contacts provides advantages and enables unique architectures that were not possible with conventional front-end-of-line transistors with both S/D contacts being on one side.
    Type: Application
    Filed: October 31, 2019
    Publication date: May 6, 2021
    Applicant: Intel Corporation
    Inventors: Wilfred Gomes, Mauro J. Kobrinsky, Abhishek A. Sharma, Tahir Ghani, Doug Ingerly, Rajesh Kumar
  • Publication number: 20210125990
    Abstract: Described herein are IC devices that include TFT based memory arrays on both sides of a layer of logic devices. An example IC device includes a support structure (e.g., a substrate) on which one or more logic devices may be implemented. The IC device further includes a first memory cell on one side of the support structure, and a second memory cell on the other side of the support structure, where each of the first memory cell and the second memory cell includes a TFT as an access transistor. Providing TFT based memory cells on both sides of a layer of logic devices allows significantly increasing density of memory cells in a memory array having a given footprint area, or, conversely, significantly reducing the footprint area of the memory array with a given memory cell density.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 29, 2021
    Applicant: Intel Corporation
    Inventors: Wilfred Gomes, Mauro J. Kobrinsky, Conor P. Puls, Kevin Fischer, Bernhard Sell, Abhishek A. Sharma, Tahir Ghani
  • Publication number: 20210111129
    Abstract: An integrated circuit includes a base with one or more semiconductor devices. An insulating material is over the base and an interconnect structure is over the base. The interconnect structure includes vertical conductors extending through the insulating material in a spaced-apart arrangement. The interconnect structure comprises a conductor and a chalcogen, the chalcogen present in an amount of up to 5 atomic percent. In some embodiments, the chalcogen is present in an amount less than 2 atomic percent or less than 1 atomic percent.
    Type: Application
    Filed: October 9, 2019
    Publication date: April 15, 2021
    Applicant: INTEL CORPORATION
    Inventors: Carl H. Naylor, Mauro J. Kobrinsky
  • Publication number: 20210111115
    Abstract: Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.
    Type: Application
    Filed: December 18, 2020
    Publication date: April 15, 2021
    Applicant: Intel Corporation
    Inventors: Patrick Morrow, Mauro J. Kobrinsky, Mark T. Bohr, Tahir Ghani, Rishabh Mehandru
  • Publication number: 20210074823
    Abstract: Techniques are disclosed for backside source/drain (S/D) replacement for semiconductor devices with metallization on both sides (MOBS). The techniques described herein provide methods to recover or otherwise facilitate low contact resistance, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some cases, the techniques include forming sacrificial S/D material and a seed layer during frontside processing of a device layer including one or more transistor devices. The device layer can then be inverted and bonded to a host wafer. A backside reveal of the device layer can then be performed via grinding, etching, and/or CMP processes. The sacrificial S/D material can then be removed through backside S/D contact trenches using the seed layer as an etch stop, followed by the formation of relatively highly doped final S/D material grown from the seed layer, to provide enhanced ohmic contact properties. Other embodiments may be described and/or disclosed.
    Type: Application
    Filed: October 28, 2020
    Publication date: March 11, 2021
    Applicant: INTEL CORPORATION
    Inventors: Glenn A. Glass, Karthik Jambunathan, Anand S. Murthy, Chandra S. Mohapatra, Patrick Morrow, Mauro J. Kobrinsky
  • Patent number: 10892337
    Abstract: Techniques are disclosed for backside source/drain (S/D) replacement for semiconductor devices with metallization on both sides (MOBS). The techniques described herein provide methods to recover or otherwise facilitate low contact resistance, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some cases, the techniques include forming sacrificial S/D material and a seed layer during frontside processing of a device layer including one or more transistor devices. The device layer can then be inverted and bonded to a host wafer. A backside reveal of the device layer can then be performed via grinding, etching, and/or CMP processes. The sacrificial S/D material can then be removed through backside S/D contact trenches using the seed layer as an etch stop, followed by the formation of relatively highly doped final S/D material grown from the seed layer, to provide enhanced ohmic contact properties. Other embodiments may be described and/or disclosed.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: January 12, 2021
    Assignee: INTEL Corporation
    Inventors: Glenn A. Glass, Karthik Jambunathan, Anand S. Murthy, Chandra S. Mohapatra, Patrick Morrow, Mauro J. Kobrinsky
  • Patent number: 10886217
    Abstract: Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: January 5, 2021
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Mauro J. Kobrinsky, Mark T. Bohr, Tahir Ghani, Rishabh Mehandru
  • Patent number: 10797139
    Abstract: Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 6, 2020
    Assignee: Intel Corporation
    Inventors: Patrick Morrow, Mauro J. Kobrinsky, Kimin Jun, Il-Seok Son, Paul B. Fischer
  • Patent number: 10734412
    Abstract: Techniques are disclosed for backside contact resistance reduction for semiconductor devices with metallization on both sides (MOBS). In some embodiments, the techniques described herein provide methods to recover low contact resistance that would otherwise be present with making backside contacts, thereby reducing or eliminating parasitic external resistance that degrades transistor performance. In some embodiments, the techniques include adding an epitaxial deposition of very highly doped crystalline semiconductor material in backside contact trenches to provide enhanced ohmic contact properties. In some cases, a backside source/drain (S/D) etch-stop layer may be formed below the replacement S/D regions of the one or more transistors formed on the transfer wafer (during frontside processing), such that when backside contact trenches are being formed, the backside S/D etch-stop layer may help stop the backside contact etch process before consuming a portion or all of the S/D material.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan, Chandra S. Mohapatra, Mauro J. Kobrinsky, Patrick Morrow