Patents by Inventor Maxim S. Shatalov

Maxim S. Shatalov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10199535
    Abstract: A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: February 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 10199536
    Abstract: A method of fabricating a device using a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions. A device including one or more of these features also is provided.
    Type: Grant
    Filed: June 26, 2017
    Date of Patent: February 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 10199537
    Abstract: A semiconductor structure comprising a buffer structure and a set of semiconductor layers formed adjacent to a first side of the buffer structure is provided. The buffer structure can have an effective lattice constant and a thickness such that an overall stress in the set of semiconductor layers at room temperature is compressive and is in a range between approximately 0.1 GPa and 2.0 GPa. The buffer structure can be grown using a set of growth parameters selected to achieve the target effective lattice constant a, control stresses present during growth of the buffer structure, and/or control stresses present after the semiconductor structure has cooled.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: February 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 10199531
    Abstract: A heterostructure for use in fabricating an optoelectronic device is provided. The heterostructure includes a layer, such as an n-type contact or cladding layer, that includes thin sub-layers inserted therein. The thin sub-layers can be spaced throughout the layer and separated by intervening sub-layers fabricated of the material for the layer. The thin sub-layers can have a distinct composition from the intervening sub-layers, which alters stresses present during growth of the heterostructure.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: February 5, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Daniel Billingsley, Robert M. Kennedy, Wenhong Sun, Rakesh Jain, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Publication number: 20190030477
    Abstract: A system for providing ultraviolet treatment of volatile organic compounds (VOCs) is disclosed. The system can include a first gas conduit to carry a stream of gas having VOCs and a second gas conduit to carry a second stream of gas containing a partial pressure of water vapor. A gas treatment unit can be coupled to the first gas conduit and the second gas conduit. The gas treatment unit can form hydroxyl radicals from the water vapor in the stream of gas carried by the second gas conduit and inject the radicals in the first gas conduit to decrease the presence of the VOCs. The gas treatment unit can include a photocatalyst component and at least one ultraviolet radiation source to irradiate the photocatalyst component with ultraviolet radiation. To this extent, the irradiated photocatalyst component disassociates the gas containing the water vapor to form the hydroxyl radicals.
    Type: Application
    Filed: June 5, 2018
    Publication date: January 31, 2019
    Applicant: Sensor Electronic Technology, Inc.
    Inventor: Maxim S. Shatalov
  • Publication number: 20190019917
    Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 17, 2019
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur, Brandon Robinson
  • Patent number: 10181398
    Abstract: A solution for fabricating a group III nitride heterostructure and/or a corresponding device is provided. The heterostructure can include a nucleation layer, which can be grown on a lattice mismatched substrate using a set of nucleation layer growth parameters. An aluminum nitride layer can be grown on the nucleation layer using a set of aluminum nitride layer growth parameters. The respective growth parameters can be configured to result in a target type and level of strain in the aluminum nitride layer that is conducive for growth of additional heterostructure layers resulting in strains and strain energies not exceeding threshold values which can cause relaxation and/or dislocation formation.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: January 15, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Wenhong Sun, Alexander Dobrinsky, Maxim S. Shatalov, Michael Shur, Remigijus Gaska
  • Patent number: 10172968
    Abstract: Ultraviolet radiation is directed within a storage area formed of a plurality of layers including an outer ultraviolet reflective layer, an inner ultraviolet transparent layer, and a layer located between the outer ultraviolet reflective layer and the inner ultraviolet transparent layer. The refractive index of the layer between the outer ultraviolet reflective layer and the inner ultraviolet transparent layer is less than the refractive index of the inner ultraviolet transparent layer. A set of ultraviolet radiation sources generate ultraviolet radiation directed at a set of items located within the storage area.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: January 8, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Maxim S. Shatalov, Timothy James Bettles, Yuri Bilenko, Saulius Smetona, Alexander Dobrinsky, Remigijus Gaska
  • Patent number: 10178726
    Abstract: A solid-state light source (SSLS) structure with integrated control. In one embodiment, a SSLS control circuit can be integrated with a SSLS structure formed from a multiple of SSLSs. The SSLS control circuit controls the total operating current of the SSLS structure to within a predetermined total operating current limit by selectively limiting the current in individual SSLSs or in groups of SSLSs as each are turned on according to a sequential order. The SSLS control circuit limits the current in each of the individual SSLSs or groups of SSLSs as function of the saturation current of the SSLSs. In one embodiment, the individual SSLSs or groups of SSLSs has a turn on voltage corresponding to a voltage causing a preceding SSLS or group of SSLSs in the sequential order to saturate current.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: January 8, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Michael Shur, Alexander Dobrinsky, Maxim S. Shatalov
  • Patent number: 10177534
    Abstract: A device is provided in which a light emitting semiconductor structure is excited by an electron beam that impacts a region of a lateral surface of the light emitting semiconductor structure at an angle to the normal of the lateral surface that is non-zero. The non-zero angle can be configured to cause excitation in a desired region of the light emitting semiconductor structure. The device can include wave guiding layer(s) and/or other features to improve the light generation and/or operation of the device.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: January 8, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Michael Shur, Alexander Dobrinsky
  • Publication number: 20190006553
    Abstract: Semiconductor structures formed with annealing for use in the fabrication of optoelectronic devices. The semiconductor structures can include a substrate, a nucleation layer and a buffer layer. The nucleation layer and the buffer layer can be epitaxially grown and then annealed. The temperature of the annealing of the nucleation layer and the buffer layer is greater than the temperature of the epitaxial growth of the layers. The annealing reduces the dislocation density in any subsequent layers that are added to the semiconductor structures. A desorption minimizing layer epitaxially grown on the buffer layer can be used to minimize desorption during the annealing of the layer which also aids in curtailing dislocation density and cracks in the semiconductor structures.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 3, 2019
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Maxim S. Shatalov
  • Publication number: 20180374986
    Abstract: Fabrication of a heterostructure, such as a group III nitride heterostructure, for use in an optoelectronic device is described. The heterostructure can be epitaxially grown on a sacrificial layer, which is located on a substrate structure. The sacrificial layer can be at least partially decomposed using a laser. The substrate structure can be completely removed from the heterostructure or remain attached thereto. One or more additional solutions for detaching the substrate structure from the heterostructure can be utilized. The heterostructure can undergo additional processing to form the optoelectronic device.
    Type: Application
    Filed: August 13, 2018
    Publication date: December 27, 2018
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Michael Shur, Alexander Dobrinsky, Maxim S. Shatalov
  • Patent number: 10164147
    Abstract: A light emitting heterostructure including one or more fine structure regions is provided. The light emitting heterostructure can include a plurality of barriers alternating with a plurality of quantum wells. One or more of the barriers and/or quantum wells includes a fine structure region. The fine structure region includes a plurality of subscale features arranged in at least one of: a growth or a lateral direction.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: December 25, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Wenhong Sun, Alexander Dobrinsky, Maxim S. Shatalov, Jinwei Yang, Michael Shur, Remigijus Gaska
  • Patent number: 10158044
    Abstract: A solution for fabricating a semiconductor structure is provided. The semiconductor structure includes a plurality of semiconductor layers grown over a substrate using a set of epitaxial growth periods. During each epitaxial growth period, a first semiconductor layer having one of: a tensile stress or a compressive stress is grown followed by growth of a second semiconductor layer having the other of: the tensile stress or the compressive stress directly on the first semiconductor layer.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: December 18, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Remigijus Gaska, Michael Shur
  • Patent number: 10153396
    Abstract: A device having a layer with a patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers with a high concentration of aluminum, is provided. The patterned surface can include a substantially flat top surface and a plurality of stress reducing regions, such as openings. The substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the stress reducing regions can have a characteristic size between approximately 0.1 microns and approximately five microns and a depth of at least 0.2 microns. A layer of group-III nitride material can be grown on the first layer and have a thickness at least twice the characteristic size of the stress reducing regions.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: December 11, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Rakesh Jain, Wenhong Sun, Jinwei Yang, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur, Remigijus Gaska
  • Patent number: 10147848
    Abstract: An optoelectronic device with a multi-layer contact is described. The optoelectronic device can include a n-type semiconductor layer having a surface. A mesa can be located over a first portion of the surface of the n-type semiconductor layer and have a mesa boundary. A n-type contact region can be located over a second portion of the surface of the n-type semiconductor contact layer entirely distinct from the first portion, and be at least partially defined by the mesa boundary. A first n-type metallic contact layer can be located over at least a portion of the n-type contact region in proximity of the mesa boundary, where the first n-type metallic contact layer forms an ohmic contact with the n-type semiconductor layer. A second n-type metallic contact layer can be located over a second portion of the n-type contact region, where the second n-type metallic contact layer is formed of a reflective metallic material.
    Type: Grant
    Filed: October 3, 2016
    Date of Patent: December 4, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Mikhail Gaevski, Maxim S. Shatalov, Alexander Dobrinsky, Michael Shur
  • Patent number: 10147854
    Abstract: A solution for packaging an optoelectronic device using an ultraviolet transparent polymer is provided. The ultraviolet transparent polymer material can be placed adjacent to the optoelectronic device and/or a device package on which the optoelectronic device is mounted. Subsequently, the ultraviolet transparent polymer material can be processed to cause the ultraviolet transparent polymer material to adhere to the optoelectronic device and/or the device package. The ultraviolet transparent polymer can be adhered in a manner that protects the optoelectronic device from the ambient environment.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: December 4, 2018
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Saulius Smetona, Alexander Dobrinsky, Michael Shur, Mikhail Gaevski
  • Publication number: 20180323345
    Abstract: An optoelectronic device with a multi-layer contact is described. The optoelectronic device can include an n-type semiconductor layer having a surface. A mesa can be located over a first portion of the surface of the n-type semiconductor layer and have a mesa boundary, which has a shape including a plurality of interconnected fingers. The n-type semiconductor layer can have a shape at least partially defined by the mesa boundary. A first n-type contact layer can be located adjacent to another portion of the n-type semiconductor contact layer, where the first n-type contact layer forms an ohmic contact with the n-type semiconductor layer. A second contact layer can be located over a second portion of the n-type semiconductor contact layer, where the second contact layer is formed of a reflective material.
    Type: Application
    Filed: July 2, 2018
    Publication date: November 8, 2018
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Alexander Dobrinsky, Maxim S. Shatalov, Mikhail Gaevski, Michael Shur
  • Publication number: 20180323071
    Abstract: A semiconductor structure, such as a group III nitride-based semiconductor structure is provided. The semiconductor structure includes a cavity containing semiconductor layer. The cavity containing semiconductor layer can have a thickness greater than two monolayers and a multiple cavities. The cavities can have a characteristic size of at least one nanometer and a characteristic separation of at least five nanometers.
    Type: Application
    Filed: June 29, 2018
    Publication date: November 8, 2018
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Maxim S. Shatalov, Jinwei Yang, Wenhong Sun, Rakesh Jain, Michael Shur, Remigijus Gaska
  • Publication number: 20180315886
    Abstract: A heterostructure, such as a group III nitride heterostructure, for use in an optoelectronic device is described. The heterostructure can include a sacrificial layer, which is located on a substrate structure. The sacrificial layer can be at least partially decomposed using a laser. The substrate structure can be completely removed from the heterostructure or remain attached thereto. One or more additional solutions for detaching the substrate structure from the heterostructure can be utilized. The heterostructure can undergo additional processing to form the optoelectronic device.
    Type: Application
    Filed: June 20, 2018
    Publication date: November 1, 2018
    Applicant: Sensor Electronic Technology, Inc.
    Inventors: Mikhail Gaevski, Alexander Dobrinsky, Maxim S. Shatalov, Michael Shur