Patents by Inventor Mayank T. Bulsara

Mayank T. Bulsara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9508724
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: November 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mayank T. Bulsara, Anthony J. Lochtefeld, Matthew T. Currie
  • Publication number: 20150380414
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Application
    Filed: September 11, 2015
    Publication date: December 31, 2015
    Inventors: Mayank T. Bulsara, Anthony J. Lochtefeld, Matthew T. Currie
  • Patent number: 9153591
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: October 6, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mayank T. Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
  • Publication number: 20150060972
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Application
    Filed: November 5, 2014
    Publication date: March 5, 2015
    Inventors: Mayank T. Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
  • Patent number: 8890226
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mayank T. Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
  • Patent number: 8441055
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: May 14, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mayank T. Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
  • Patent number: 7494881
    Abstract: Misfit dislocations are selectively placed in layers formed over substrates. Thicknesses of layers may be used to define distances between misfit dislocations and surfaces of layers formed over substrates, as well as placement of misfit dislocations and dislocation arrays with respect to devices subsequently formed on the layers.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: February 24, 2009
    Assignee: AmberWave Systems Corporation
    Inventors: Anthony J. Lochtefeld, Christopher Leitz, Matthew T. Currie, Mayank T. Bulsara
  • Patent number: 6495868
    Abstract: InxGa1−xAs structures with compositionally graded buffers grown with organometallic vapor phase epitaxy (OMPVE) on GaAs substrates. A semiconductor structure and a method of processing such a structure including providing a substrate of GaAs; and epitaxially growing a relaxed graded layer of InxGa1−xAs at a temperature ranging upwards from about 600° C.
    Type: Grant
    Filed: March 13, 2001
    Date of Patent: December 17, 2002
    Assignee: Massachusetts Institute of Technology
    Inventors: Eugene A. Fitzgerald, Mayank T. Bulsara
  • Publication number: 20020030227
    Abstract: A DMOS field effect transistor fabricated from a SiGe heterostructure and a method of fabricating same. The heterostructure includes a strained Si layer on a relaxed, low dislocation density SiGe template. In an exemplary embodiment, the DMOS FET includes a SiGe/Si heterostructure on top of a bulk Si substrate. The heterostructure includes a SiGe graded layer, a SiGe cap of uniform composition layer, and a strained Si channel layer. In accordance with another embodiment, the invention provides a heterostructure for a DMOS transistor, and method of fabricating same, including a monocrystalline Si substrate, a relaxed uniform composition SiGe layer on the substrate; a first strained-Si channel layer on the uniform composition SiGe layer, a SiGe cap layer on the strained-Si channel layer, and a second strained-Si layer on the cap layer.
    Type: Application
    Filed: January 18, 2001
    Publication date: March 14, 2002
    Inventors: Mayank T. Bulsara, Eugene A. Fitzgerald
  • Publication number: 20010040244
    Abstract: InxGa1−xAs structures with compositionally graded buffers grown with organometallic vapor phase epitaxy (OMPVE) on GaAs substrates. A semiconductor structure and a method of processing such a structure including providing a substrate of GaAs; and epitaxially growing a relaxed graded layer of InxGa1−xAs at a temperature ranging upwards from about 600° C.
    Type: Application
    Filed: March 13, 2001
    Publication date: November 15, 2001
    Inventors: Eugene A. Fitzgerald, Mayank T. Bulsara
  • Patent number: 6232138
    Abstract: InxGa1−xAs structures with compositionally graded buffers grown with organometallic vapor phase epitaxy (OMPVE) on GaAs substrates. A semiconductor structure and a method of processing such a structure including providing a substrate of GaAs; and epitaxially growing a relaxed graded layer of InxGa1−xAs at a temperature ranging upwards from about 600° C.
    Type: Grant
    Filed: November 24, 1998
    Date of Patent: May 15, 2001
    Assignee: Massachusetts Institute of Technology
    Inventors: Eugene A. Fitzgerald, Mayank T. Bulsara