Patents by Inventor Meenakshisundaram Ramanathan

Meenakshisundaram Ramanathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250089228
    Abstract: Integrated circuit (IC) structures that include static random-access memory (SRAM) and that are fabricated using gate contact patterning after source/drain (S/D) metallization are disclosed. An example IC structure includes a transistor comprising an S/D region and a gate electrode material, an S/D contact in electrical contact with the S/D region, and a gate contact in electrical contact with the gate electrode material. The S/D contact includes a first electrically conductive material, the gate contact includes a second electrically conductive material, and a portion of the second electrically conductive material is in electrical contact with a portion of the first electrically conductive material, wherein an average grain size or orientation in the portion of the first electrically conductive material is different from an average grain size or orientation in the portion of the second electrically conductive material.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 13, 2025
    Applicant: Intel Corporation
    Inventors: Meenakshisundaram Ramanathan, Krishna Ganesan, John Crocker, Akitomo Matsubayashi, Jianhua Yin, Reken Patel
  • Publication number: 20240355890
    Abstract: Techniques are provided herein to form semiconductor devices that include a conductive bridge between topside contacts on adjacent source or drain regions. The conductive bridge extends through a dielectric wall that separates the adjacent source or drain regions. In an example, a first semiconductor device includes a first gate structure around or otherwise on a first semiconductor region (or channel region) that extends from a first source or drain region, and a second adjacent semiconductor device includes a second gate structure around or otherwise on a second semiconductor region that extends from a second source or drain region. A conductive bridge connects a first conductive contact on a top surface of the first source or drain region with a second conductive contact on a top surface of the adjacent second source or drain region through a dielectric wall that otherwise separates the conductive contacts.
    Type: Application
    Filed: April 20, 2023
    Publication date: October 24, 2024
    Applicant: Intel Corporation
    Inventors: Leonard P. Guler, Shengsi Liu, Saurabh Acharya, Baofu Zhu, Meenakshisundaram Ramanathan, Charles H. Wallace, Ankit Kirit Lakhani
  • Publication number: 20240355891
    Abstract: Techniques are provided herein to form semiconductor devices that include a conductive bridge between topside contacts on adjacent source or drain regions. The conductive bridge extends through a dielectric wall that separates the adjacent source or drain regions. In an example, a first semiconductor device includes a first gate structure around or otherwise on a first semiconductor region (or channel region) that extends from a first source or drain region, and a second adjacent semiconductor device includes a second gate structure around or otherwise on a second semiconductor region that extends from a second source or drain region. A conductive bridge connects a first conductive contact on a top surface of the first source or drain region with a second conductive contact on a top surface of the adjacent second source or drain region through a dielectric wall that otherwise separates the conductive contacts.
    Type: Application
    Filed: June 25, 2024
    Publication date: October 24, 2024
    Applicant: Intel Corporation
    Inventors: Leonard P. Guler, Shengsi Liu, Saurabh Acharya, Baofu Zhu, Meenakshisundaram Ramanathan, Charles H. Wallace, Ankit Kirit Lakhani
  • Publication number: 20240321872
    Abstract: Techniques to form an integrated circuit having a gate cut between adjacent pairs of semiconductor devices. At least one of those adjacent pairs of semiconductor devices includes a conductive link (e.g., a bridge) through the gate cut to connect the adjacent gates together. In an example, neighboring semiconductor devices each include a semiconductor region extending between a source region and a drain region, and a gate structure extending over the semiconductor regions of the neighboring semiconductor devices. A gate cut is present between each pair of neighboring semiconductor devices thus interrupting the gate structure and isolating the gate of one semiconductor device from the gate of the other semiconductor device. A conductive link extends over a given gate cut to electrically connect the adjacent gate electrodes together. A dielectric layer extends over the bridged gate electrodes and the conductive link, and may have different thicknesses over those respective features.
    Type: Application
    Filed: March 23, 2023
    Publication date: September 26, 2024
    Applicant: Intel Corporation
    Inventors: Leonard P. Guler, Shengsi Liu, Saurabh Acharya, Thomas Obrien, Krishna Ganesan, Ankit Kirit Lakhani, Prabhjot Kaur Luthra, Nidhi Khandelwal, Clifford J. Engel, Baofu Zhu, Meenakshisundaram Ramanathan