Patents by Inventor Megumi Ishiduki
Megumi Ishiduki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160268298Abstract: A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.Type: ApplicationFiled: September 10, 2015Publication date: September 15, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Tadashi IGUCHI, Murato Kawai, Toru Matsuda, Hisashi Kato, Megumi Ishiduki
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Publication number: 20160240554Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: ApplicationFiled: April 28, 2016Publication date: August 18, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KIDOH, Masaru KITO, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Hideaki AOCHI
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Publication number: 20160190152Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: ApplicationFiled: March 8, 2016Publication date: June 30, 2016Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KITO, Masaru KIDOH, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Junya MATSUNAMI, Tomoko FUJIWARA, Hideaki AOCHI, Ryouhei KlRISAWA, Yoshimasa MIKAJIRI, Shigeto OOTA
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Patent number: 9373634Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The second insulating film seals the hole near an interface of the insulating layer and the select gate. The second insulating film is provided on a side wall of the channel body with a space left in the hole above the select gate. The method can include burying a semiconductor film in the space, in addition, forming a conductive film in contact with the channel body.Type: GrantFiled: May 8, 2015Date of Patent: June 21, 2016Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuru Sato, Masaru Kito, Megumi Ishiduki, Ryota Katsumata
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Patent number: 9356042Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: GrantFiled: March 25, 2015Date of Patent: May 31, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
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Patent number: 9318503Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: GrantFiled: August 24, 2015Date of Patent: April 19, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Patent number: 9312134Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: GrantFiled: January 8, 2014Date of Patent: April 12, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Publication number: 20160071926Abstract: According to one embodiment, a semiconductor memory device includes a stacked body including a plurality of electrode layers separately stacked each other; a plurality of columnar sections provided in the stacked body and extending in a stacking direction of the stacked body; and a first insulating section separating the stacked body. The respective columnar sections include a semiconductor body extending in the stacking direction; and a charge storage film provided between the semiconductor body and the plurality of electrode layers. The first insulating section includes a first air gap.Type: ApplicationFiled: March 6, 2015Publication date: March 10, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Soichirou KITAZAKI, Mitsuru Sato, Megumi Ishiduki
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Publication number: 20150364489Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: ApplicationFiled: August 24, 2015Publication date: December 17, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki FUKUZUMI, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Patent number: 9147575Abstract: A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.Type: GrantFiled: January 8, 2014Date of Patent: September 29, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kito, Masaru Kidoh, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Hideaki Aochi, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Publication number: 20150249094Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The second insulating film seals the hole near an interface of the insulating layer and the select gate. The second insulating film is provided on a side wall of the channel body with a space left in the hole above the select gate. The method can include burying a semiconductor film in the space, in addition, forming a conductive film in contact with the channel body.Type: ApplicationFiled: May 8, 2015Publication date: September 3, 2015Applicant: Kabushiki Kaisha ToshibaInventors: Mitsuru SATO, Masaru KITO, Megumi ISHIDUKI, Ryota KATSUMATA
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Publication number: 20150200204Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: ApplicationFiled: March 25, 2015Publication date: July 16, 2015Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki FUKUZUMI, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
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Patent number: 9054132Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. The second insulating film seals the hole near an interface of the insulating layer and the select gate. The second insulating film is provided on a side wall of the channel body with a space left in the hole above the select gate. The method can include burying a semiconductor film in the space, in addition, forming a conductive film in contact with the channel body.Type: GrantFiled: June 28, 2013Date of Patent: June 9, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Mitsuru Sato, Masaru Kito, Megumi Ishiduki, Ryota Katsumata
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Patent number: 9035374Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: GrantFiled: April 7, 2014Date of Patent: May 19, 2015Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki Fukuzumi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Hiroyasu Tanaka, Yosuke Komori, Megumi Ishiduki, Hideaki Aochi
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Patent number: 9029934Abstract: A nonvolatile semiconductor memory device includes: forming a stacked body by alternately stacking a plurality of interlayer insulating films and a plurality of control gate electrodes; forming a through-hole extending in a stacking direction in the stacked body; etching a portion of the interlayer insulating film facing the through-hole via the through-hole to remove the portion; forming a removed portion; forming a first insulating film on inner faces of the through-hole and the portion in which the interlayer insulating films are removed; forming a floating gate electrode in the portion in which the interlayer insulating films are removed; forming a second insulating film so as to cover a portion of the floating gate electrode facing the through-hole; and burying a semiconductor pillar in the through-hole.Type: GrantFiled: April 17, 2013Date of Patent: May 12, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Kito, Masaru Kidoh, Tomoko Fujiwara, Yosuke Komori, Megumi Ishiduki, Hiroyasu Tanaka, Yoshiaki Fukuzumi, Ryota Katsumata, Ryouhei Kirisawa, Junya Matsunami, Hideaki Aochi
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Patent number: 8916921Abstract: A plurality of a first conductive layers are provided at a certain interval L in a vertical direction, with a dielectric sandwiched therebetween. The certain interval L is set so that the first dielectric has an equivalent oxide thickness DEOT that satisfies the following relation (1). Dsio2<DEOT<Dk??(1) Dsio2 denotes a thickness of the dielectric when the dielectric is composed of silicon oxide with a minimum thickness that can withstand a maximum voltage to be applied to the first conductive layers. Dk denotes such an equivalent oxide thickness of a first dielectric that provides the resistance value Rsio2. The resistance value Rsio2 being defined as a resistance value of the first semiconductor layer for each of the first conductive layers when the dielectric is composed of silicon oxide and has a film thickness of Dsio2.Type: GrantFiled: February 12, 2010Date of Patent: December 23, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Hiroyasu Tanaka, Hideaki Aochi, Ryota Katsumata, Masaru Kidoh, Masaru Kito, Yoshiaki Fukuzumi, Yosuke Komori, Megumi Ishiduki
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Patent number: 8884355Abstract: A nonvolatile semiconductor memory device includes: a stacked structural unit including a plurality of electrode films and a plurality of inter-electrode insulating films alternately stacked in a first direction; a first selection gate electrode stacked on the stacked structural unit in the first direction; a first semiconductor pillar piercing the stacked structural unit and the first selection gate electrode in the first direction; a first memory unit provided at an intersection of each of the electrode films and the first semiconductor pillar; and a first selection gate insulating film provided between the first semiconductor pillar and the first selection gate electrode, the first selection gate electrode including a first silicide layer provided on a face of the first selection gate electrode perpendicular to the first direction.Type: GrantFiled: March 19, 2010Date of Patent: November 11, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yosuke Komori, Hideaki Aochi, Ryota Katsumata, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Hiroyasu Tanaka, Megumi Ishiduki, Tomoko Fujiwara, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota
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Publication number: 20140284685Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes: a stacked body including each of a plurality of electrode layers and each of a plurality of insulating layers stacked alternately; a first interlayer insulating film; a select gate electrode; a second interlayer insulating film; a pair of semiconductor layers; a first insulating film; a second insulating film; a third interlayer insulating film; a first contact electrode connected to one upper end of the pair of semiconductor layers; a second contact electrode connected to the other upper end of the pair of semiconductor layers; a third contact electrode connected to the second contact electrode; a first interconnect layer connected to the first contact electrode; and a second interconnect layer connected to the third contact electrode.Type: ApplicationFiled: August 19, 2013Publication date: September 25, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Yoshiro SHIMOJO, Tsuneo Uenaka, Megumi Ishiduki, Mitsuru Sato
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Publication number: 20140217493Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.Type: ApplicationFiled: April 7, 2014Publication date: August 7, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Yoshiaki FUKUZUMI, Ryota KATSUMATA, Masaru KIDOH, Masaru KITO, Hiroyasu TANAKA, Yosuke KOMORI, Megumi ISHIDUKI, Hideaki AOCHI
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Patent number: RE45840Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.Type: GrantFiled: July 9, 2014Date of Patent: January 12, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Ryota Katsumata, Hideaki Aochi, Hiroyasu Tanaka, Masaru Kito, Yoshiaki Fukuzumi, Masaru Kidoh, Yosuke Komori, Megumi Ishiduki, Junya Matsunami, Tomoko Fujiwara, Ryouhei Kirisawa, Yoshimasa Mikajiri, Shigeto Oota