Abstract: An integrated circuit includes first and second arrays of resistors, and a plurality of interface circuits. Each resistor in the first array is electrically coupled between a corresponding first input conductive line among a plurality of first or second input conductive lines, and a corresponding first output conductive line among a plurality of first or second output conductive lines. Each resistor in the second array is electrically coupled between a corresponding second input conductive line among a plurality of second input conductive lines, and a corresponding second output conductive line among a plurality of second output conductive lines. Each interface circuit is electrically coupled between a corresponding first output conductive line and a corresponding second input conductive line. Each interface circuit is configured to receive a signal on the corresponding first output conductive line, and apply an analog voltage corresponding to the signal to the corresponding second input conductive line.

Abstract: An interface circuit includes an integrator circuit and a buffer circuit. The integrator circuit is configured to be electrically coupled to a column of memory cells, receive a signal corresponding to a sum of currents flowing through the memory cells of the column, and integrate the signal over time to generate an intermediate voltage. The buffer circuit is electrically coupled to an output of the integrator circuit to receive the intermediate voltage, and is configured to be electrically coupled to a row of further memory cells, generate an analog voltage corresponding to the intermediate voltage, and output the analog voltage to the further memory cells of the row.

Abstract: Systems and methods are provided for controlling power down of an overdrive low drop out regulator circuits. The system is designed with a low dropout regulator circuit configured to operate in a safe operating area range of operation with very low current. The circuit contains a regulator, a current boost, and a power down switch. The current boost is responsive to a power down signal, generally from a power distribution board. The circuit is fabricated such that the low dropout regulator circuit with the current boost operates with minimum current pull while maintaining safe operating area range of operation. The safe operating area range of operation is maintained during various design operations, normal operations, and power down. This regulator circuit may be designed without a middle level voltage or high-ground.

Abstract: A method includes: selectively generating a first current by a first current generating circuit according to a first control signal; generating a second current by a second current generating circuit; and comparing a first input signal and a second input signal at a common node to generate an output signal according to the first current, the second current, and a second control signal. The second control signal and the first control signal are in-phase with each other.

Abstract: Systems and methods are provided for controlling power down of an overdrive low drop out regulator circuits. The system is designed with a low dropout regulator circuit configured to operate in a safe operating area range of operation with very low current. The circuit contains a regulator, a current boost, and a power down switch. The current boost is responsive to a power down signal, generally from a power distribution board. The circuit is fabricated such that the low dropout regulator circuit with the current boost operates with minimum current pull while maintaining safe operating area range of operation. The safe operating area range of operation is maintained during various design operations, normal operations, and power down. This regulator circuit may be designed without a middle level voltage or high-ground.

Abstract: An integrated circuit includes first and second arrays of resistors, and a plurality of interface circuits. Each resistor in the first array is electrically coupled between a corresponding first input conductive line among a plurality of first or second input conductive lines, and a corresponding first output conductive line among a plurality of first or second output conductive lines. Each resistor in the second array is electrically coupled between a corresponding second input conductive line among a plurality of second input conductive lines, and a corresponding second output conductive line among a plurality of second output conductive lines. Each interface circuit is electrically coupled between a corresponding first output conductive line and a corresponding second input conductive line. Each interface circuit is configured to receive a signal on the corresponding first output conductive line, and apply an analog voltage corresponding to the signal to the corresponding second input conductive line.

Abstract: Disclosed are resistance control units based on gates, switches and/or memory cells. In one embodiment, a resistance control unit of a neural network formed on an integrated circuit (IC) is disclosed. The resistance control unit includes: a plurality of resistors coupled between a first node and a second node of the neural network; a plurality of switches coupled to the plurality of resistors and configured for controlling a current flowing from the first node to the second node; and a plurality of memory cells configured for generating a digital output. The plurality of switches can be controlled by the digital output.

Abstract: A method includes: selectively generating a first current by a first current generating circuit according to a first control signal; generating a second current by a second current generating circuit; and comparing a first input signal and a second input signal at a common node to generate an output signal according to the first current, the second current, and a second control signal. The second control signal and the first control signal are in-phase with each other.

Abstract: Systems and methods are provided for controlling power down of an overdrive low drop out regulator circuits. The system is designed with a low dropout regulator circuit configured to operate in a safe operating area range of operation with very low current. The circuit contains a regulator, a current boost, and a power down switch. The current boost is responsive to a power down signal, generally from a power distribution board. The circuit is fabricated such that the low dropout regulator circuit with the current boost operates with minimum current pull while maintaining safe operating area range of operation. The safe operating area range of operation is maintained during various design operations, normal operations, and power down. This regulator circuit may be designed without a middle level voltage or high-ground.

Abstract: A comparing device includes a first current generating circuit arranged to selectively generate a first current and a second current different from the first current, according to a first control signal. The comparing device also includes a comparing circuit having a common node coupled to the first current generating circuit for comparing a first input signal and a second input signal to generate an output signal according to the first current, the second current, and a second control signal. The second control signal and the first control signal are in-phase with each other.

Abstract: A comparing device includes a first current generating circuit arranged to selectively generate a first current and a second current different from the first current, according to a first control signal. The comparing device also includes a comparing circuit having a common node coupled to the first current generating circuit for comparing a first input signal and a second input signal to generate an output signal according to the first current, the second current, and a second control signal. The second control signal and the first control signal are in-phase with each other.

Abstract: An ACD device comprises a comparator having an output, a first input, and a second input. The ADC includes a successive approximation register (SAR) configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage Vref=M*VDD, where M<1. The ADC also includes a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator.

Abstract: A comparing device includes: a first current generating circuit arranged to selectively generate a first current according to a first control signal; a second current generating circuit arranged to generate a second current; and a comparing circuit having a common node coupled to the first current generating circuit and the second current generating circuit for comparing a first input signal and a second input signal to generate an output signal according to the first current, the second current, and a second control signal.

Abstract: An ACD device comprises a comparator having an output, a first input, and a second input. The ADC includes a successive approximation register (SAR) configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage Vref=N*VDD, where N<1. The ADC also includes a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator.

Abstract: An ADC device comprises a comparator having an output, a first input, and a second input. And the ADC includes a SAR configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage. The ADC also includes a DAC configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator. The DAC further includes a capacitor network coupled to the first input having a redistribution capacitor coupled to a first voltage that is greater than the reference voltage such that a ratio N is equal to the reference voltage divided by the first voltage. The DAC also includes one or more first capacitors also coupled to the first voltage, where at least one first capacitor is associated with the MSB.

Abstract: A sample and hold (S/H) circuit includes a capacitor coupling a sample node to a first voltage and an input line carrying a signal from an input. The S/H circuit also can include one or more transistors coupling the input line to the sample node. The S/H circuit also can include a switch coupled to one or more sources or drains of the one or more transistors and to a second voltage. The S/H circuit also can include a hold circuit coupled to the switch and to one or more gates of the one or more transistors, the hold circuit configured to open, during a sample period, the input line between the input and the sample node.

Abstract: An ADC device comprises a comparator having an output, a first input, and a second input. And the ADC includes a SAR configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage. The ADC also includes a DAC configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator. The DAC further includes a capacitor network coupled to the first input having a redistribution capacitor coupled to a first voltage that is greater than the reference voltage such that a ratio N is equal to the reference voltage divided by the first voltage. The DAC also includes one or more first capacitors also coupled to the first voltage, where at least one first capacitor is associated with the MSB.

Abstract: A sample and hold (S/H) circuit includes a capacitor coupling a sample node to a first voltage and an input line carrying a signal from an input. The S/H circuit also can include one or more transistors coupling the input line to the sample node. The S/H circuit also can include a switch coupled to one or more sources or drains of the one or more transistors and to a second voltage. The S/H circuit also can include a hold circuit coupled to the switch and to one or more gates of the one or more transistors, the hold circuit configured to open, during a sample period, the input line between the input and the sample node.

Abstract: A thermal sensor comprises a converter circuit, a counting circuit, and a ratio calculator. The converter circuit is configured to convert a temperature-independent signal into a first frequency signal, and to convert a temperature-dependent signal into a second frequency signal. The counting circuit is configured to receive at least one of the first frequency signal and the second frequency signal, to count a predetermined number of pulses of the first frequency signal, and to count a number of pulses of the second frequency signal for a time period corresponding to the counting of the predetermined number of pulses of the first frequency signal. The ratio calculator is configured to calculate a ratio based on the predetermined number of pulses of the first frequency signal and the counted number of pulses of the second frequency signal.

Abstract: A method includes measuring a first voltage across a test diode on a semiconductor wafer while injecting a first current into the test diode, measuring a second voltage across the test diode while injecting a second current into the test diode, and determining temperature of a region proximate the test diode according to difference between the first voltage and the second voltage.