Abstract: Counting the number of set and unset bits in an n-bit data word or stream of data is most efficient in applications where the data can be characterized as sparsely populated (bits mostly or all unset/0) and/or heavily populated (bits mostly or all set/1). In these populations, processing can be linearly proportional to the smaller number of differing bit values resulting in compute time and resource savings. In any population, the operations of the bit counting methods, systems, apparata and computer program products described are bounded by the number of bits counted in the data word/stream. The described operations can be used for determining whether further processing of the data stream is required as well as the extent of that processing.

Abstract: Counting the number of set and unset bits in an n-bit data word or stream of data is most efficient in applications where the data can be characterized as sparsely populated (bits mostly or all unset/0) and/or heavily populated (bits mostly or all set/1). In these populations, processing can be linearly proportional to the smaller number of differing bit values resulting in compute time and resource savings. In any population, the operations of the bit counting methods, systems, apparata and computer program products described are bounded by the number of bits counted in the data word/stream. The described operations can be used for determining whether further processing of the data stream is required as well as the extent of that processing.

Abstract: A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Abstract: A method and apparatus for moving data in a parallel processing system (3). In one embodiment, a single instruction accesses one significant bit of information from each element in processing element array (80) and combines these bits into one designated element in global register file (50). The ordering of bits in vectors of global register file (50) associates each bit with an element of processing element array (80). Another single instruction distinguishes significant bit information from a particular vector in global register file (50) and transfers that information to an associated bit in storage circuits associated with each element in processing element array (80).

Abstract: The present invention, which is implemented in a data processing system, includes a method for performing a fuzzy logic operation, wherein the steps are: (1) performing a rule evaluation process on a plurality of fuzzy input values, wherein one or more of the plurality of fuzzy input values has a lower limit (zero) value, and wherein the rule evaluation process (i) implements a rulebase including a plurality of rules associating a plurality of fuzzy inputs with a plurality of fuzzy outputs, (ii) results in one or more fuzzy output values, and (iii) further includes processing the one or more of the fuzzy input values having the lower limit value with respect to the rulebase, and (2) processing the fuzzy input values having a non-lower limit value with respect to the rulebase, the processing of the fuzzy input values having the non-lower limit value performed separately from the processing of the one or more of the fuzzy input values having the lower limit value.

Abstract: A method for complex data movement in a multi-processor data processing system. In one embodiment, the multi-processor data processing system (10) includes an array (12) of data processors (50-65), a plurality of edge interface circuits (14,16), and a bus interface controller (22). In an alternate embodiment, multiprocessor data processing system (210) includes an array (212) of data processors (250-258), a plurality of edge interface circuits (214-217), and a bus interface controller (222). The data processing systems (10,210) are capable of performing complex data movement patterns between the processors (50-65,250-258) and the corresponding edge interface circuits (14, 16, 214-217), such as a transpose pattern, a ping-pong pattern, and a checkerboard pattern.