Abstract: A package structure including a semiconductor die, a warpage control layer, an insulating encapsulant and a redistribution layer is provided. The semiconductor die has an active surface and a backside surface opposite to the active surface. The warpage control layer is disposed on the backside surface of the semiconductor die, wherein the warpage control layer comprises a material having a Young's Modulus of 100 GPa or more. The insulating encapsulant is encapsulating the semiconductor die and the warpage control layer. The redistribution layer is located on the insulating encapsulant and over the active surface of the semiconductor die.

Abstract: There is provided a pupil tracking device including an active light source, an image sensor and a processing unit. The active light source emits light toward an eyeball alternatively in a first brightness value and a second brightness value. The image sensor captures a first brightness image corresponding to the first brightness value and a second brightness image corresponding to the second brightness value. The processing unit identifies a brightest region at corresponding positions of the first brightness image and the second brightness image as an active light image.

Abstract: A semiconductor device includes a first package component and a second package component. The first package component has a first die formed on a first substrate. A second package component has a second die formed on a second substrate. A thermal isolation material is attached on the first die, wherein the thermal isolation material thermally insulates the second die from the first die, and the thermal isolation material has a thermal conductivity of from about 0.024 W/mK to about 0.2 W/mK. A first set of conductive elements couples the first package component to the second package component.

Abstract: A semiconductor device including a chip package, a dielectric structure and a first antenna pattern is provided. The dielectric structure disposed on the chip package and includes a cavity and a vent in communication with the cavity. The first antenna pattern disposed on the dielectric structure, wherein the chip package is electrically coupled to the first antenna pattern, and the cavity of the dielectric structure is disposed between the chip package and the first antenna pattern. A manufacturing method of a semiconductor device is also provided.

Abstract: A package structure including a semiconductor die, a warpage control layer, an insulating encapsulant and a redistribution layer is provided. The semiconductor die has an active surface and a backside surface opposite to the active surface. The warpage control layer is disposed on the backside surface of the semiconductor die, wherein the warpage control layer comprises a material having a Young's Modulus of 100 GPa or more. The insulating encapsulant is encapsulating the semiconductor die and the warpage control layer. The redistribution layer is located on the insulating encapsulant and over the active surface of the semiconductor die.

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a package. The method includes coupling a first package component to a second package component using a first set of conductive elements. A first polymer-comprising material is formed over the second package component and surrounding the first set of conductive elements. The first polymer-comprising material is cured to solidify the first polymer-comprising material. A part of the first polymer-comprising material is removed to expose an upper surface of the second package component. The second package component is coupled to a third package component using a second set of conductive elements that are formed onto the upper surface of the second package component.

Abstract: A method includes attaching a first semiconductor package on a carrier, wherein the first semiconductor package comprises a plurality of stacked semiconductor dies and a plurality of contact pads, depositing a first molding compound layer over the carrier, wherein the first semiconductor package is embedded in the first molding compound layer, forming a plurality of vias over the plurality of contact pads, attaching a semiconductor die on the first molding compound layer, depositing a second molding compound layer over the carrier, wherein the semiconductor die and the plurality of vias are embedded in the second molding compound layer, forming an interconnect structure over the second molding compound layer and forming a plurality of bumps over the interconnect structure.

Abstract: An integrated fan-out (InFO) package includes at least one die, a plurality of conductive structures, an encapsulant, an enhancement layer, and a redistribution structure. The die has an active surface and includes a plurality of conductive posts on the active surface. The conductive structures surround the die. The encapsulant partially encapsulates the die. The enhancement layer is over the encapsulant. A top surface of the enhancement layer is substantially coplanar with top surfaces of the conductive posts and the conductive structures. A material of the enhancement layer is different from a material of the encapsulant. A roughness of an interface between the encapsulant and the enhancement layer is larger than a roughness of the top surface of the enhancement layer. The redistribution structure is over the enhancement layer and is electrically connected to the conductive structures and the die.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a chip, a molding compound, and a dielectric layer. The chip has a connector thereon. The molding compound encapsulates the chip, wherein a surface of the molding compound is substantially lower than an active surface of the chip. The dielectric layer is disposed over the chip and the molding compound, wherein the dielectric layer has a planar surface, and a material of the dielectric layer is different from a material of the molding compound.

Abstract: An integrated fan-out (InFO) package includes at least one die, a plurality of conductive structures, an encapsulant, an enhancement layer, and a redistribution structure. The die has an active surface and includes a plurality of conductive posts on the active surface. The conductive structures surround the die. The encapsulant partially encapsulates the die. The enhancement layer is over the encapsulant. A top surface of the enhancement layer is substantially coplanar with top surfaces of the conductive posts and the conductive structures. A material of the enhancement layer is different from a material of the encapsulant. A roughness of an interface between the encapsulant and the enhancement layer is larger than a roughness of the top surface of the enhancement layer. The redistribution structure is over the enhancement layer and is electrically connected to the conductive structures and the die.

Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.

Abstract: The present disclosure relates to a package-on-package structure providing mechanical strength and warpage control. In some embodiments, the package-on-package structure includes a first set of conductive elements coupling a first package component to a second package component. A first molding material is arranged on the first package component. The first molding material surrounds the first set of conductive elements and outer sidewalls of the second package component and has a top surface below a top surface of the second package component. The stacked integrated chip structure further includes a second set of conductive elements that couples the second package component to a third package component.

Abstract: A device comprises a first package component, and a first metal trace and a second metal trace on a top surface of the first package component. The device further includes a dielectric mask layer covering the top surface of the first package component, the first metal trace and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace. The device also includes a second package component and an interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, wherein the solder bump contacts the first metal trace in the opening of the dielectric mask layer.

Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.

Abstract: A system and method for applying an underfill is provided. An embodiment comprises applying an underfill to a substrate and patterning the underfill. Once patterned other semiconductor devices, such as semiconductor dies or semiconductor packages may then be attached to the substrate through the underfill, with electrical connections from the other semiconductor devices extending into the pattern of the underfill.

Abstract: Methods of packaging semiconductor devices and packaged semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a dam structure on dies proximate edge regions of the dies. A molding material is disposed around the dies, and a top portion of the molding material and a top portion of the dam structure are removed.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package includes a chip, a molding compound, and a dielectric layer. The chip has a connector thereon. The molding compound encapsulates the chip, wherein a surface of the molding compound is substantially lower than an active surface of the chip. The dielectric layer is disposed over the chip and the molding compound, wherein the dielectric layer has a planar surface, and a material of the dielectric layer is different from a material of the molding compound.

Abstract: A device comprises a first package component, and a first metal trace and a second metal trace on a top surface of the first package component. The device further includes a dielectric mask layer covering the top surface of the first package component, the first metal trace and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace. The device also includes a second package component and an interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, wherein the solder bump contacts the first metal trace in the opening of the dielectric mask layer.