Patents by Inventor Meng-Wei Chiang

Meng-Wei Chiang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220012402
    Abstract: A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.
    Type: Application
    Filed: July 1, 2021
    Publication date: January 13, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ming-Fa Chen, Sen-Bor Jan, Meng-Wei Chiang
  • Patent number: 11080455
    Abstract: A method includes generating an integrated circuit (IC) layout design and manufacturing an IC based on the IC layout design. Generating the IC layout design includes generating a pattern of a first shallow trench isolation (STI) region and a pattern of a through substrate via (TSV) region within the first STI region; a pattern of a second STI region surrounding the first STI region, the second STI region includes a first and second layout region, the second layout region being separated from the first STI region by the first layout region, first active regions of a group of dummy devices being defined within the first layout region, and second active regions of a group of active devices being defined within the second layout region; and patterns of first gates of the group of dummy devices in the first layout region, each of the first active regions having substantially identical dimension in a first direction.
    Type: Grant
    Filed: July 9, 2020
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ming-Fa Chen, Sen-Bor Jan, Meng-Wei Chiang
  • Patent number: D952631
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: May 24, 2022
    Assignee: HTC Corporation
    Inventors: Meng-Sheng Chiang, Chin-Wei Chou, Yien-Chun Kuo