Patents by Inventor Meng-Wei Chou
Meng-Wei Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240105705Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.Type: ApplicationFiled: December 1, 2023Publication date: March 28, 2024Inventors: Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin
-
Patent number: 11901307Abstract: Semiconductor devices and method of manufacture are provided. In embodiments a conductive connector is utilized to provide an electrical connection between a substrate and an overlying shield. The conductive connector is placed on the substrate and encapsulated with an encapsulant. Once encapsulated, an opening is formed through the encapsulant to expose a portion of the conductive connector. The shield is deposited through the encapsulant to make an electrical connection to the conductive connector.Type: GrantFiled: June 12, 2020Date of Patent: February 13, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Yao Chuang, Meng-Wei Chou, Shin-Puu Jeng
-
Patent number: 11855059Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.Type: GrantFiled: June 24, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin
-
Patent number: 11854955Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.Type: GrantFiled: July 23, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
-
Publication number: 20230361015Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.Type: ApplicationFiled: July 13, 2023Publication date: November 9, 2023Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
-
Publication number: 20230307251Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.Type: ApplicationFiled: May 26, 2023Publication date: September 28, 2023Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
-
Patent number: 11699598Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.Type: GrantFiled: December 14, 2020Date of Patent: July 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou
-
Patent number: 11682599Abstract: A method for forming a chip package structure is provided. The method includes disposing a chip over a redistribution structure. The method includes forming a molding layer over the redistribution structure and adjacent to the chip. The method includes partially removing the molding layer to form a trench in the molding layer, and the trench is spaced apart from the chip.Type: GrantFiled: November 26, 2018Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
-
Publication number: 20230105359Abstract: In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.Type: ApplicationFiled: December 12, 2022Publication date: April 6, 2023Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
-
Patent number: 11527474Abstract: In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.Type: GrantFiled: September 28, 2020Date of Patent: December 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
-
Publication number: 20220359421Abstract: Semiconductor devices and method of manufacture are provided. In embodiments a conductive connector is utilized to provide an electrical connection between a substrate and an overlying shield. The conductive connector is placed on the substrate and encapsulated with an encapsulant. Once encapsulated, an opening is formed through the encapsulant to expose a portion of the conductive connector. The shield is deposited through the encapsulant to make an electrical connection to the conductive connector.Type: ApplicationFiled: July 21, 2022Publication date: November 10, 2022Inventors: Po-Yao Chuang, Meng-Wei Chou, Shin-Puu Jeng
-
Publication number: 20220344317Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.Type: ApplicationFiled: June 24, 2022Publication date: October 27, 2022Inventors: Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin
-
Publication number: 20220216192Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.Type: ApplicationFiled: March 22, 2022Publication date: July 7, 2022Inventors: Shin-Puu Jeng, Techi Wong, Po-Yao Chuang, Shuo-Mao Chen, Meng-Wei Chou
-
Patent number: 11380666Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.Type: GrantFiled: October 12, 2020Date of Patent: July 5, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin
-
Patent number: 11296065Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.Type: GrantFiled: June 15, 2020Date of Patent: April 5, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shin-Puu Jeng, Techi Wong, Po-Yao Chuang, Shuo-Mao Chen, Meng-Wei Chou
-
Publication number: 20210391314Abstract: An embodiment a structure including a first semiconductor device bonded to a first side of a first redistribution structure by first conductive connectors, the first semiconductor device comprising a first plurality of passive elements formed on a first substrate, the first redistribution structure comprising a plurality of dielectric layers with metallization patterns therein, the metallization patterns of the first redistribution structure being electrically coupled to the first plurality of passive elements, a second semiconductor device bonded to a second side of the first redistribution structure by second conductive connectors, the second side of the first redistribution structure being opposite the first side of the first redistribution structure, the second semiconductor device comprising a second plurality of passive elements formed on a second substrate, the metallization patterns of the first redistribution structure being electrically coupled to the second plurality of passive elements.Type: ApplicationFiled: June 15, 2020Publication date: December 16, 2021Inventors: Shin-Puu Jeng, Techi Wong, Po-Yao Chuang, Shuo-Mao Chen, Meng-Wei Chou
-
Publication number: 20210351118Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.Type: ApplicationFiled: July 23, 2021Publication date: November 11, 2021Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
-
Publication number: 20210305170Abstract: Semiconductor devices and method of manufacture are provided. In embodiments a conductive connector is utilized to provide an electrical connection between a substrate and an overlying shield. The conductive connector is placed on the substrate and encapsulated with an encapsulant. Once encapsulated, an opening is formed through the encapsulant to expose a portion of the conductive connector. The shield is deposited through the encapsulant to make an electrical connection to the conductive connector.Type: ApplicationFiled: June 12, 2020Publication date: September 30, 2021Inventors: Po-Yao Chuang, Meng-Wei Chou, Shin-Puu Jeng
-
Patent number: 11075151Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.Type: GrantFiled: August 31, 2018Date of Patent: July 27, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
-
Publication number: 20210134611Abstract: A semiconductor device and method that comprise a first dielectric layer over a encapsulant that encapsulates a via and a semiconductor die is provided. A redistribution layer is over the first dielectric layer, and a second dielectric layer is over the redistribution layer, and the second dielectric layer comprises a low-temperature polyimide material.Type: ApplicationFiled: December 14, 2020Publication date: May 6, 2021Inventors: Zi-Jheng Liu, Yu-Hsiang Hu, Jo-Lin Lan, Sih-Hao Liao, Chen-Cheng Kuo, Hung-Jui Kuo, Chung-Shi Liu, Chen-Hua Yu, Meng-Wei Chou