Patents by Inventor Mi Hyun Hwang

Mi Hyun Hwang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210287816
    Abstract: An apparatus for treating waste of a nuclear reactor pressure vessel includes: a suction unit inserted into the nuclear reactor pressure vessel through a plurality of through-pipes passing through a lower portion of the nuclear reactor pressure vessel to suck waste inside the nuclear reactor pressure vessel; a waste treatment part connected to the suction unit to treat the waste; and a lower collection part connected to the waste treatment part to be positioned under the nuclear reactor pressure vessel with the suction unit therebetween.
    Type: Application
    Filed: July 3, 2019
    Publication date: September 16, 2021
    Inventors: Young Hwan HWANG, Mi-Hyun LEE, Seok-Ju HWANG, Cheon-Woo KIM
  • Publication number: 20210280330
    Abstract: A nuclear reactor dismantlement system according to an embodiment includes bio-protective concrete including a first space into which a reactor is inserted and a second space that is connected to the first space and is expanded in the first space, a moving device that is positioned in the second space and moves the reactor, and a cutting device that is positioned in the second space and cuts the reactor.
    Type: Application
    Filed: July 3, 2019
    Publication date: September 9, 2021
    Inventors: Young Hwan HWANG, Mi-Hyun LEE, Sung-Hoon HONG, Cheon-Woo KIM
  • Patent number: 11107546
    Abstract: Disclosed are a memory device and an operating method thereof, and the memory device includes a plurality of first data lines, a plurality of second data lines, a common redundant memory region coupled to at least one repair line of the second data lines, a plurality of normal memory regions coupled to the first data lines in common, and coupled in common to the remaining the second data lines excluding the repair line, and a repair circuit coupled to the first and second data lines, and suitable for replacing at least one defective memory cell in the normal memory regions with at least one redundant memory cell in the common redundant memory region by shifting some or all of the first data lines to some or all of the second data lines, based on a row address, a column address and a region address.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: August 31, 2021
    Assignee: SK hynix Inc.
    Inventors: Mi-Hyun Hwang, Jong-Chern Lee
  • Patent number: 11031067
    Abstract: A semiconductor memory device includes a controller for sequentially activating first and second control signals and activating a third control signal during an amplification period, in a pseudo cryogenic temperature, a first driver for driving a first power source line with a first voltage during an initial period of the amplification period, based on the first control signal, a second driver for driving the first power source line with a second voltage during a later period of the amplification period, based on the second control signal, a third driver for driving a second power source line with a third voltage during the amplification period, based on the third control signal, and a sense amplifier for primarily amplifying a voltage difference between a data line pair using the first and third voltages during the initial period, and secondarily amplifying the difference using the second and third voltages during the later period.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: June 8, 2021
    Assignee: SK hynix Inc.
    Inventor: Mi-Hyun Hwang
  • Patent number: 10895998
    Abstract: A storage device for outputting a pattern for analyzing input data includes: a data receiver configured to sequentially receive a plurality of input data, each including a pattern for identifying data for a corresponding input period of a plurality of input periods; a pattern determiner configured to set, as a reference pattern, a pattern included in any one data among the plurality of input data, and generate a control signal based on whether correspondence data including the same pattern as the reference pattern is input; and a data storage configured to store the plurality of input data in a sequence in which the plurality of input data are input, and, when the correspondence data is stored, output capture data that are stored data including the correspondence data based on the control signal.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: January 19, 2021
    Assignee: SK hynix Inc.
    Inventors: Mi Hyun Hwang, Jong Chern Lee
  • Publication number: 20200388344
    Abstract: Disclosed are a memory device and an operating method thereof, and the memory device includes a plurality of first data lines, a plurality of second data lines, a common redundant memory region coupled to at least one repair line of the second data lines, a plurality of normal memory regions coupled to the first data lines in common, and coupled in common to the remaining the second data lines excluding the repair line, and a repair circuit coupled to the first and second data lines, and suitable for replacing at least one defective memory cell in the normal memory regions with at least one redundant memory cell in the common redundant memory region by shifting some or all of the first data lines to some or all of the second data lines, based on a row address, a column address and a region address.
    Type: Application
    Filed: December 24, 2019
    Publication date: December 10, 2020
    Inventors: Mi-Hyun HWANG, Jong-Chern LEE
  • Publication number: 20200356495
    Abstract: A memory module includes: a plurality of memories, wherein each of the memories comprises: an encryption key storage circuit suitable for storing an encryption key; an address encryption circuit suitable for generating an encrypted address by encrypting an address transferred from a memory controller by using the encryption key stored in the encryption key storage circuit; and a cell array accessed by the encrypted address, wherein the encryption key storage circuits of the memories store different encryption keys.
    Type: Application
    Filed: December 27, 2019
    Publication date: November 12, 2020
    Inventors: Woongrae KIM, Sang-Kwon LEE, Jung-Hyun KIM, Jong-Hyun PARK, Jong-Ho SON, Mi-Hyun HWANG, Jeong-Tae HWANG
  • Publication number: 20200265889
    Abstract: A semiconductor memory device includes a controller for sequentially activating first and second control signals and activating a third control signal during an amplification period, in a pseudo cryogenic temperature, a first driver for driving a first power source line with a first voltage during an initial period of the amplification period, based on the first control signal, a second driver for driving the first power source line with a second voltage during a later period of the amplification period, based on the second control signal, a third driver for driving a second power source line with a third voltage during the amplification period, based on the third control signal, and a sense amplifier for primarily amplifying a voltage difference between a data line pair using the first and third voltages during the initial period, and secondarily amplifying the difference using the second and third voltages during the later period.
    Type: Application
    Filed: November 14, 2019
    Publication date: August 20, 2020
    Inventor: Mi-Hyun HWANG
  • Publication number: 20200073583
    Abstract: A storage device for outputting a pattern for analyzing input data includes: a data receiver configured to sequentially receive a plurality of input data, each including a pattern for identifying data for a corresponding input period of a plurality of input periods; a pattern determiner configured to set, as a reference pattern, a pattern included in any one data among the plurality of input data, and generate a control signal based on whether correspondence data including the same pattern as the reference pattern is input; and a data storage configured to store the plurality of input data in a sequence in which the plurality of input data are input, and, when the correspondence data is stored, output capture data that are stored data including the correspondence data based on the control signal.
    Type: Application
    Filed: April 23, 2019
    Publication date: March 5, 2020
    Inventors: Mi Hyun HWANG, Jong Chern LEE
  • Patent number: 10153013
    Abstract: A data output buffer may be provided. The data output buffer may include a pull-up circuit configured to output a pull-up feedback signal by pull-up driving an output node. The data output buffer may include a pull-up driver configured to output the pull-up drive signal by driving a pull-up signal, and selectively activate the pull-up drive signal based on the pull-up feedback signal. The data output buffer may include a pull-down circuit configured to output a pull-down feedback signal by pull-down driving the output node based on a pull-down drive signal. The data output buffer may include a pull-down driver configured to output the pull-down drive signal by driving a pull-down signal, and selectively activate the pull-down drive signal based on the pull-down feedback signal.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: December 11, 2018
    Assignee: SK hynix Inc.
    Inventor: Mi Hyun Hwang
  • Publication number: 20180233179
    Abstract: A data output buffer may be provided. The data output buffer may include a pull-up circuit configured to output a pull-up feedback signal by pull-up driving an output node. The data output buffer may include a pull-up driver configured to output the pull-up drive signal by driving a pull-up signal, and selectively activate the pull-up drive signal based on the pull-up feedback signal. The data output buffer may include a pull-down circuit configured to output a pull-down feedback signal by pull-down driving the output node based on a pull-down drive signal. The data output buffer may include a pull-down driver configured to output the pull-down drive signal by driving a pull-down signal, and selectively activate the pull-down drive signal based on the pull-down feedback signal.
    Type: Application
    Filed: July 10, 2017
    Publication date: August 16, 2018
    Applicant: SK hynix Inc.
    Inventor: Mi Hyun HWANG
  • Patent number: 9911505
    Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output a clock signal, a test mode signal and command address signals. The second semiconductor device may repeatedly write and read out data into and from a plurality of memory cells sequentially selected by addresses that are sequentially counted or may repeatedly write and read out the data into and from specific memory cells selected by a specific address among the addresses, according to the clock signal and the command address signals in response to the test mode signal.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: March 6, 2018
    Assignee: SK hynix Inc.
    Inventors: Chul Moon Jung, Mi Hyun Hwang
  • Patent number: 9672893
    Abstract: A semiconductor device includes a decoded signal generation circuit suitable for executing a counting operation to generate a decoded signal in response to an oscillation signal during a refresh section, a refresh pulse generation circuit suitable for generating a refresh pulse for executing a refresh operation in response to the decoded signal and a temperature code, and a reset pulse generation circuit suitable for generating a reset pulse initializing the decoded signal in response to the refresh pulse.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: June 6, 2017
    Assignee: SK hynix Inc.
    Inventors: Chul Moon Jung, Mi Hyun Hwang, Man Keun Kang, Sang Kwon Lee
  • Publication number: 20170133086
    Abstract: A semiconductor device includes a decoded signal generation circuit suitable for executing a counting operation to generate a decoded signal in response to an oscillation signal during a refresh section, a refresh pulse generation circuit suitable for generating a refresh pulse for executing a refresh operation in response to the decoded signal and a temperature code, and a reset pulse generation circuit suitable for generating a reset pulse initializing the decoded signal in response to the refresh pulse.
    Type: Application
    Filed: February 11, 2016
    Publication date: May 11, 2017
    Inventors: Chul Moon JUNG, Mi Hyun HWANG, Man Keun KANG, Sang Kwon LEE
  • Publication number: 20170038428
    Abstract: A semiconductor system may include a first semiconductor device and a second semiconductor device. The first semiconductor device may output a clock signal, a test mode signal and command address signals. The second semiconductor device may repeatedly write and read out data into and from a plurality of memory cells sequentially selected by addresses that are sequentially counted or may repeatedly write and read out the data into and from specific memory cells selected by a specific address among the addresses, according to the clock signal and the command address signals in response to the test mode signal.
    Type: Application
    Filed: November 20, 2015
    Publication date: February 9, 2017
    Inventors: Chul Moon JUNG, Mi Hyun HWANG
  • Publication number: 20160217846
    Abstract: A semiconductor device may include a refresh controller and a bank active signal generator. The refresh controller may be suitable for generating a level signal, setting a level of the level signal in response to a refresh pulse signal while operating in a test mode, and suitable for receiving a refresh flag signal and generating a first period signal and a second period signal in response to the level signal. The bank active signal generator may be suitable for generating bank active signals for a first bank group in response to the first period signal, and generating bank active signals for a second bank group in response to the second period signal.
    Type: Application
    Filed: May 6, 2015
    Publication date: July 28, 2016
    Inventors: Chul Moon JUNG, Man Keun KANG, Mi Hyun HWANG
  • Patent number: 9397642
    Abstract: A latch circuit includes a first PMOS transistor suitable for pull-up driving a second node based on a voltage of a first node, a first NMOS transistor suitable for pull-down driving the second node based on a voltage of the first node, a second PMOS transistor suitable for pull-up driving the first node based on a voltage of the second node, a second NMOS transistor suitable for pull-down driving the first node based on a voltage of the second node, a first separation element suitable for electrically separating the first NMOS transistor from the second node when the first PMOS transistor is turned on, and a second separation element suitable for electrically separating the second NMOS transistor from the first node when the second PMOS transistor is turned on.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: July 19, 2016
    Assignee: SK Hynix Inc.
    Inventors: Hae-Rang Choi, Mi-Hyun Hwang
  • Publication number: 20160164504
    Abstract: A latch circuit includes a first PMOS transistor suitable for pull-up driving a second node based on a voltage of a first node, a first NMOS transistor suitable for pull-down driving the second node based on a voltage of the first node, a second PMOS transistor suitable for pull-up driving the first node based on a voltage of the second node, a second NMOS transistor suitable for pull-down driving the first node based on a voltage of the second node, a first separation element suitable for electrically separating the first NMOS transistor from the second node when the first PMOS transistor is turned on, and a second separation element suitable for electrically separating the second NMOS transistor from the first node when the second PMOS transistor is turned on.
    Type: Application
    Filed: April 3, 2015
    Publication date: June 9, 2016
    Inventors: Hae-Rang CHOI, Mi-Hyun HWANG
  • Patent number: 9275693
    Abstract: The semiconductor memory device may include a power control signal generator and a sense amplifier circuit. The power control signal generator may generate a first power control signal in response to a detection signal generated from detecting a level of a power supply voltage signal. The sense amplifier circuit may generate a first power signal driven to have a first drive voltage in response to the first power control signal. The sense amplifier circuit may sense and amplify a level of a bit line using the first power signal as a power supply voltage.
    Type: Grant
    Filed: December 4, 2014
    Date of Patent: March 1, 2016
    Assignee: SK Hynix Inc.
    Inventor: Mi Hyun Hwang
  • Patent number: 9208850
    Abstract: A semiconductor memory device includes a plurality of normal word lines and a plurality of redundancy word lines which are disposed adjacent to the normal word lines, a detection block suitable for detecting a first word line whose active history satisfies a predetermined condition and a second word line adjacent to the first word line as a target word line and a target neighboring word line, among the normal word lines and the redundancy word lines, and a control block suitable for sequentially refreshing the normal word lines and the redundancy word lines whenever a refresh command is applied, and additionally refreshing the target word line, the target neighboring word line and a normal word line adjacent to the redundancy word lines among the normal word lines.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: December 8, 2015
    Assignee: SK Hynix Inc.
    Inventor: Mi-Hyun Hwang