Abstract: Embodiments of the present invention are directed to managing a shared high-level cache for dual clusters of fully connected integrated circuit multiprocessors. An example of a computer-implemented method includes: providing a drawer comprising a plurality of clusters, each of the plurality of clusters comprising a plurality of processors; providing a shared cache integrated circuit to manage a shared cache memory among the plurality of clusters; receiving, by the shared cache integrated circuit, an operation of one of a plurality of operation types from one of the plurality of processors; and processing, by the shared cache integrated circuit, the operation based at least in part on the operation type of the operation according to a set of rules for processing the operation type.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for ownership tracking updates across multiple simultaneous operations. A non-limiting example of the computer-implemented method includes receiving, by a cache directory control circuit, a message to update a cache directory entry. The method further includes, in response, updating, by the cache directory control circuit, the cache directory entry, and generating a reverse compare signal including an updated ownership vector of a memory line corresponding to the cache directory entry. The method further includes sending the reverse compare signal to a cache controller associated with the cache directory entry.

Abstract: Embodiments of the present invention are directed to a computer-implemented method for ownership tracking updates across multiple simultaneous operations. A non-limiting example of the computer-implemented method includes receiving, by a cache directory control circuit, a message to update a cache directory entry. The method further includes, in response, updating, by the cache directory control circuit, the cache directory entry, and generating a reverse compare signal including an updated ownership vector of a memory line corresponding to the cache directory entry. The method further includes sending the reverse compare signal to a cache controller associated with the cache directory entry.

Abstract: In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.

Abstract: A computer implemented method for avoiding false activation of hang avoidance mechanisms of a system is provided. The computer implemented method includes receiving, by a nest of the system, rejects from a processor core of the system. The rejects are issued based on a cache line being locked by the processor core. The computer implemented method includes accumulating the rejects by the nest. The computer implemented method includes determining, by the nest, when an amount of the rejects accumulated by the nest has met or exceeded a programmable threshold. The computer implemented method also includes triggering, by the nest, a global reset to counters of the hang avoidance mechanisms of a system in response to the amount meeting or exceeding the programmable threshold.

Abstract: Methods, devices, and systems for monitoring heart rate variability (HRV) are presented. The HRV monitoring systems and devices are adapted to give immediate feedback to the subject concerning their current condition and any pertinent changes in their condition. The HRV monitoring systems and devices detect, analyze, and assess HRV against a pre-determined application, user needs, against pre-determined limits, or user specific baselines or a combination of both pre-determined limits and user specific baselines. They also have the ability to provide real time notifications based on the system's assessment of a user's heart rate, HRV and changes in the HRV.

Abstract: Embodiments of the present invention are directed to hot cache line arbitration. An example of a computer-implemented method for hot cache line arbitration includes receiving a request for exclusive access to a cache line from a requestor of a drawer in a processing system. The method further includes bringing the cache line to a local cache of the drawer. The method further includes invalidating copies of the cache line in the processing system. The method further includes loading a remote fetch address register (RFAR) controller on other drawers in the processing system, wherein the RFAR comprises a local pending flag and a remote pending flag.

Abstract: Embodiments of the present invention are directed to hot cache line arbitration. An example of a computer-implemented method for hot cache line arbitration includes detecting, by a processing device, a hot cache line scenario. The computer-implemented method further includes tracking, by the processing device, hot cache line requests from requesters to determine subsequent satisfaction of the requests. The computer-implemented method further includes facilitating, by the processing device, servicing of the requests according to hierarchy of the requestors.

Abstract: In an approach for purging an address range from a cache, a processor quiesces a computing system. Cache logic issues a command to purge a section of a cache to higher level memory, wherein the command comprises a starting storage address and a range of storage addresses to be purged. Responsive to each cache of the computing system activating the command, cache logic ends the quiesce of the computing system. Subsequent to ending the quiesce of the computing system, Cache logic purges storage addresses from the cache, based on the command, to the higher level memory.

Abstract: Methods, devices, and systems for monitoring heart rate variability (HRV) are presented. The HRV monitoring systems and devices are adapted to give immediate feedback to the subject concerning their current condition and any pertinent changes in their condition. The HRV monitoring systems and devices detect, analyze, and assess HRV against a pre-determined application or user need. They also have the ability to provide real time notifications based on the system's assessment of a user's heart HRV and changes in the HRV.

Abstract: A protective collapsible shield is provided. The protective collapsible shield may include a first panel, a second panel and a third panel. The first and second panels each have a rectangular protrusion or lip extending from a bottom edge. The third panel includes slots for housing the first panel and the second panel. The third panel further includes snapping straps for securing the first and second panels in the slots when the protective collapsible shield is in a retracted state. The third panel further includes multiple locking mechanisms. Each of the locking mechanisms includes a cylindrical rod, a handle fastened to the cylindrical rod and a housing for receiving the cylindrical rod. The locking mechanisms engage with the first and second rectangular protrusions to secure the first and second panels in the slots when the protective collapsible shield is in an extended state.

Abstract: In an approach for taking corrupt portions of cache offline during runtime, a notification of a section of a cache to be taken offline is received, wherein the section includes one or more sets in one or more indexes of the cache. An indication is associated with each set of the one or more sets in a first index of the one or more indexes, wherein the indication marks the respective set as unusable for future operations. Data is purged from the one or more sets in the first index of the cache. Each set of the one or more sets in the first index is marked as invalid.

Abstract: In an approach for taking corrupt portions of cache offline during runtime, a notification of a section of a cache to be taken offline is received, wherein the section includes one or more sets in one or more indexes of the cache. An indication is associated with each set of the one or more sets in a first index of the one or more indexes, wherein the indication marks the respective set as unusable for future operations. Data is purged from the one or more sets in the first index of the cache. Each set of the one or more sets in the first index is marked as invalid.

Abstract: Methods, devices, and systems for monitoring heart rate variability (HRV). The HRV monitoring systems and devices are adapted to give immediate feedback to the subject concerning their current condition and any pertinent changes in their condition. The HRV monitoring systems and devices detect, analyze, and assess HRV against a pre-determined application or user need. They also have the ability to provide real time notifications based on the system's assessment of a user's heart HRV and changes in the HRV.

Abstract: A compressor may include a housing, a piston, and a cylinder head assembly. The housing defines a cylinder and a first valve seat defining a recess. The piston is movable within the cylinder to define a compression chamber. The cylinder head assembly is mounted on the housing and includes a valve plate, a suction valve, a discharge valve and a head cover. The valve plate may be mounted to the mounting surface and may include a suction plenum, a suction passage providing fluid communication between the suction plenum and the cylinder, and a discharge passage. The suction valve can seat on the first valve seat to allow fluid flow through the suction passage. The head cover may include a discharge chamber and an integrally formed guide post extending into the discharge chamber. The guide post may include a pocket that receives a discharge valve stem for reciprocation therein.

Abstract: Methods, devices, and systems for monitoring heart rate variability (HRV). The HRV monitoring systems and devices are adapted to give immediate feedback to the subject concerning their current condition and any pertinent changes in their condition. The HRV monitoring systems and devices detect, analyze, and assess HRV against a pre-determined application or user need. They also have the ability to provide real time notifications based on the system's assessment of a user's heart HRV and changes in the HRV.

Abstract: In an approach for taking corrupt portions of cache offline during runtime, a notification of a section of a cache to be taken offline is received, wherein the section includes one or more sets in one or more indexes of the cache. An indication is associated with each set of the one or more sets in a first index of the one or more indexes, wherein the indication marks the respective set as unusable for future operations. Data is purged from the one or more sets in the first index of the cache. Each set of the one or more sets in the first index is marked as invalid.

Abstract: In an approach for taking corrupt portions of cache offline during runtime, a notification of a section of a cache to be taken offline is received, wherein the section includes one or more sets in one or more indexes of the cache. An indication is associated with each set of the one or more sets in a first index of the one or more indexes, wherein the indication marks the respective set as unusable for future operations. Data is purged from the one or more sets in the first index of the cache. Each set of the one or more sets in the first index is marked as invalid.

Abstract: A method, system, and/or computer program product for dynamic array masking is provided. Dynamic array masking includes, during execution of computer instructions that access a cache memory, detecting an error condition in a portion of the cache memory. The portion of the cache memory contains an array macro. Dynamic array masking, during the execution of the computer instructions that access a cache memory, further includes dynamically setting mask bits to indicate the error condition in the portion of the cache memory and preventing subsequent writes to the portion of the cache memory in accordance with the dynamically set mask bits. Embodiments also include evicting cache entries from the portion of the cache memory. This evicting can include performing a cache purge operation for the cache entries corresponding to the dynamically set mask bits.

Abstract: A multi-boundary address protection range is provided to prevent key operations from interfering with a data move performed by a dynamic memory relocation (DMR) move operation. Any key operation address that is within the move boundary address range gets rejected back to the hypervisor. Further, logic exists across a set of parallel slices to synchronize the DMR move operation as it crosses a protected boundary address range.