Patents by Inventor Michael A. Guillorn

Michael A. Guillorn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10559670
    Abstract: A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Terence B. Hook, Robert R. Robison, Reinaldo A. Vega, Rajasekhar Venigalla
  • Publication number: 20200004918
    Abstract: Methods and systems for fabricating an integrated circuit include training a machine learning model using a training set that includes known physical design layout patterns that are classified according to whether the patterns include a hotspot. It is determined whether an input physical design layout pattern includes a hotspot using the machine learning model. A hotspot localization is generated for the input physical design layout patterns. The input physical design pattern is adjusted to cure the hotspot. A circuit is fabricated in accordance with the adjusted input physical design layout pattern.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: Jing Sha, Dongbing Shao, Martin Burkhardt, Michael A. Guillorn
  • Patent number: 10522342
    Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: December 31, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Publication number: 20190393304
    Abstract: Method for forming dielectric isolation region and SiGe channels for CMOS integration of nanosheet devices generally includes epitaxially growing a multilayer structure including alternating layers of silicon, silicon germanium having a germanium content of x atomic percent and silicon germanium having a germanium content of at least 25 atomic percent greater than x. The alternating layers can be arranged and selectively patterned to form a nitride dielectric isolation region, silicon nanochannels in the NFET region, and silicon germanium nanochannels in the PFET region.
    Type: Application
    Filed: June 20, 2018
    Publication date: December 26, 2019
    Inventors: Michael A. Guillorn, Nicolas Loubet
  • Publication number: 20190377848
    Abstract: A method is presented for generating a plurality of physical design layout patterns. The method includes selecting one or more physical design layouts for neural network training, converting the plurality of physical design layout patterns into coordinate arrays, a coordinate array of the coordinate arrays including via center coordinates of vias in a physical design layout pattern of the plurality of physical design layout patterns, training, by employing the coordinate arrays, a variational autoencoder (VAE), and generating one or more new synthetic coordinate arrays by employing the trained VAE, a synthetic coordinate array of the one or more new synthetic coordinate arrays including via center coordinates of vias for a new physical design layout pattern.
    Type: Application
    Filed: June 6, 2018
    Publication date: December 12, 2019
    Inventors: Jing Sha, Michael A. Guillorn, Derren N. Dunn
  • Publication number: 20190377849
    Abstract: A method for generating physical design layout patterns includes selecting as training data a set of physical design layout patterns of features in a given layer of a given patterned structure and converting the physical design layout patterns into two-dimensional (2D) arrays comprising entries for different locations in the given layer of the given patterned structure with values representing presence of the features at the different locations. The method also includes training, utilizing the 2D arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network. The method further includes generating one or more synthetic 2D arrays utilizing the trained generator neural network of the GAN, a given synthetic 2D array comprising entries for different locations in the given layer of a new physical design layout pattern with values representing presence of the features at the different locations of the new physical design layout pattern.
    Type: Application
    Filed: June 12, 2018
    Publication date: December 12, 2019
    Inventors: Jing Sha, Michael A. Guillorn, Martin Burkhardt, Derren N. Dunn
  • Publication number: 20190370431
    Abstract: A method for generating physical design layout patterns includes the step of selecting one or more physical design layouts, a given physical design layout comprising a set of physical design layout patterns for features in at least one layer of a given patterned structure. The method also includes the step of converting the physical design layout patterns into coordinate arrays, a given coordinate array comprising feature center coordinates for the features in a given one of the physical design layout patterns. The method further includes the step of training, utilizing the coordinate arrays, a generative adversarial network (GAN) comprising discriminator and generator neural networks. The method further includes the step of generating one or more synthetic coordinate arrays utilizing the trained generator neural network of the GAN, a given one of the synthetic coordinate arrays comprising feature center coordinates of features for a new physical design layout pattern.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Inventors: Jing Sha, Michael A. Guillorn, Derren N. Dunn
  • Publication number: 20190370434
    Abstract: A computer-implemented method, computer program product, a computer processing system are provided for generating synthetic via layout patterns by a Recurrent Neural Network (RNN). The method includes generating, by a processor, a training data set of coordinate arrays that specify coordinates of vias in a set of physical design layouts for a set of integrated circuit elements. The method further includes training, by the processor, the RNN with the training data set of coordinate arrays. The method also includes generating, by the processor, using the RNN, new synthetic via patterns.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Inventors: Jing Sha, Michael A. Guillorn, Derren N. Dunn
  • Publication number: 20190370432
    Abstract: A method for generating physical design layout patterns of integrated multi-layers includes selecting as training data one or more physical design layout patterns of integrated multi-layers for features in at least two layers of a given patterned structure. The method also includes converting the physical design layout patterns into three-dimensional arrays, a given three-dimensional array comprising a set of two-dimensional arrays each representing features of one of the layers in a given physical design layout pattern. The method further includes training, utilizing the three-dimensional arrays, a generative adversarial network (GAN) comprising a discriminator neural network and a generator neural network.
    Type: Application
    Filed: June 5, 2018
    Publication date: December 5, 2019
    Inventors: Jing Sha, Michael A. Guillorn, Martin Burkhardt, Derren N. Dunn
  • Publication number: 20190370435
    Abstract: A computer-implemented method, computer program product, and computer processing system are provided for generating synthetic layout patterns. The method includes receiving, by a processor, a set of physical design layouts that include a variety of layout patterns for neural network training. The method further includes generating, by the processor, a set of training layout pattern images for the neural network training by performing automatic image capturing on the set of physical design layouts with scripts. The method also includes training, by the processor, a feedforward neural network (FFNN)-based Variational Autoencoder (VAE) with the set of training layout pattern images. The method additionally includes generating, by the processor using the FFNN-based VAE, new synthetic layout images.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 5, 2019
    Inventors: Jing Sha, Michael A. Guillorn, Derren N. Dunn
  • Patent number: 10497779
    Abstract: A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: December 3, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, William L. Nicoll, Hanfei Wang
  • Publication number: 20190346773
    Abstract: An embodiment of the invention may include a semiconductor structure for ensuring semiconductor design integrity. The semiconductor structure may include an electrical circuit necessary for the operation of the semiconductor circuit and white space having no electrical circuit. The semiconductor structure may include an optical pattern used for validating the semiconductor circuit design formed in the white space of the electrical circuit. In an embodiment of the invention, the optical pattern may include one or more deposition layers. In an embodiment of the invention, the optical pattern may include covershapes. In an embodiment of the invention, the optical pattern may be physically isolated from the electrical circuit. The optical pattern may include a Moiré pattern.
    Type: Application
    Filed: July 26, 2019
    Publication date: November 14, 2019
    Inventors: Daniel Corliss, Derren N. Dunn, Michael A. Guillorn, Shawn P. Fetterolf
  • Publication number: 20190312044
    Abstract: A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; and removing the dummy gate layer and exposing sidewalls of the fins. The fuse region is blocked to form a gate structure in the transistor region. The transistor region is blocked and the fuse region is exposed to conformally deposit a metal on exposed sidewalls of the fins. The metal is annealed to form silicided fins. Portions of the substrate are separated to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.
    Type: Application
    Filed: June 11, 2019
    Publication date: October 10, 2019
    Inventors: Karthik Balakrishnan, Michael A. Guillorn, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10438956
    Abstract: A method for integrating vertical transistors and electric fuses includes forming fins through a dielectric layer and a dummy gate stack on a substrate; thinning top portions of the fins by an etch process; epitaxially growing top source/drain regions on thinned portions of the fins in a transistor region and top cathode/anode regions on the thinned portions of the fins in a fuse region; and removing the dummy gate layer and exposing sidewalls of the fins. The fuse region is blocked to form a gate structure in the transistor region. The transistor region is blocked and the fuse region is exposed to conformally deposit a metal on exposed sidewalls of the fins. The metal is annealed to form silicided fins. Portions of the substrate are separated to form bottom source/drain regions for vertical transistors in the transistor region and bottom cathode/anode regions for fuses in the fuse region.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Michael A. Guillorn, Pouya Hashemi, Alexander Reznicek
  • Patent number: 10429743
    Abstract: An embodiment of the invention may include a method for ensuring semiconductor design integrity. The method may include analyzing a photomask design for a semiconductor circuit. The photomask may include an electrical design necessary for the operation of the semiconductor circuit, and white space, which has no electrical design. The method may include inserting an optical design into the white space of the photomask design for the semiconductor circuit. The optical design may have known optical patterns for validating the semiconductor circuit design. In an embodiment of the invention, the optical design may be physically isolated from the electrical design. In another embodiment of the invention, the optical design may comprise one or more photomask layers and overlay the electrical design. In another embodiment of the invention, the optical design may comprise covershapes.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: October 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Daniel Corliss, Derren N. Dunn, Michael A. Guillorn, Shawn P. Fetterolf
  • Patent number: 10411120
    Abstract: A method for manufacturing a semiconductor device includes forming a stacked configuration of first and second semiconductor layers on a semiconductor substrate, wherein the stacked configuration comprises a repeating arrangement of a second semiconductor layer stacked on a first semiconductor layer, forming a plurality of dummy gates spaced apart from each other on the stacked configuration, wherein the plurality of dummy gates cover a portion of the stacked configuration in a channel region, performing an implantation of a semiconductor material on exposed portions of the stacked configuration in a source/drain region, wherein the implantation increases a concentration of the semiconductor material in the exposed portions of the stacked configuration, and selectively removing first semiconductor layers having an increased concentration of the semiconductor material from the source/drain region, wherein the removed first semiconductor layers correspond in position to the first semiconductor layers in the cha
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: September 10, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robin Hsin-Kuo Chao, Michael A. Guillorn, Chi-Chun Liu, Shogo Mochizuki, Chun W. Yeung
  • Patent number: 10395922
    Abstract: A semiconductor device including a gate structure present on at least two suspended channel structures, and a composite spacer present on sidewalls of the gate structure. The composite spacer may include a cladding spacer present along a cap portion of the gate structure, and an inner spacer along the channel portion of the gate structure between adjacent channel semiconductor layers of the suspended channel structures. The inner spacer may include a crescent shape with a substantially central seam.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: August 27, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Michael A. Guillorn, Isaac Lauer, Xin Miao
  • Publication number: 20190252495
    Abstract: Semiconductor devices and methods of making the same include forming a stack of alternating layers of channel material and sacrificial material. The sacrificial material is etched away to free the layers of channel material. A gate stack is formed around the layers of channel material. At least one layer of channel material is deactivated. Source and drain regions are formed in contact with the at least one layer of active channel material.
    Type: Application
    Filed: April 26, 2019
    Publication date: August 15, 2019
    Inventors: Ruqiang Bao, Michael A. Guillorn, Terence B. Hook, Nicolas J. Loubet, Robert R. Robison, Reinaldo A. Vega, Tenko Yamashita
  • Publication number: 20190237538
    Abstract: After forming a laterally contacting pair of a semiconductor fin and a conductive strap structure overlying a deep trench capacitor embedded in a substrate and forming a gate stack straddling a body region of the semiconductor fin, source/drain regions are formed in portions the semiconductor fin located on opposite sides of the gate stack by ion implantation. Next, a metal layer is applied over the source/drain region and subsequent annealing consumes entire source/drain regions to provide fully alloyed source/drain regions. A post alloyzation ion implantation is then performed to introduce dopants into the fully alloyed source/drain regions followed by an anneal to segregate the implanted dopants at interfaces between the fully alloyed source/drain regions and the body region of the semiconductor fin.
    Type: Application
    Filed: April 8, 2019
    Publication date: August 1, 2019
    Inventors: Michael A. Guillorn, Fei Liu, Zhen Zhang
  • Publication number: 20190237541
    Abstract: Field effect transistors include a stack of nanosheets of vertically arranged channel layers. A gate stack is formed over, around, and between the vertically arranged channel layers. Spacers are formed, with at least one top pair of spacers being positioned above an uppermost channel layer. The top pair of spacers each has a curved lower portion with a curved surface in contact with the gate stack and a straight upper portion that extends vertically from the curved portion along a straight sidewall of the gate stack.
    Type: Application
    Filed: April 4, 2019
    Publication date: August 1, 2019
    Inventors: Josephine B. Chang, Michael A. Guillorn, Isaac Lauer, Xin Miao