Patents by Inventor Michael Apodaca

Michael Apodaca has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180012328
    Abstract: A mechanism for command stream processing is described. A method of embodiments, as described herein, includes fetching cache lines from a memory to fill command first in first out buffer (FIFO), wherein the fetched cachelines an overfetching of data necessary to process a command, a first parser to fetch and execute batch commands stored in the command FIFO and a second parser to fetch commands and execute the batch commands and non-batch commands stored in the command FIFO.
    Type: Application
    Filed: July 7, 2016
    Publication date: January 11, 2018
    Inventors: Jeffery S. Boles, HEMA C. NALLURI, BALAJI VEMBU, PRITAV H. SHAH, MICHAEL APODACA, MURALI RAMADOSS, LALIT K. SAPTARSHI
  • Patent number: 9864638
    Abstract: Various embodiments are presented herein that may allow an application direct access to graphical processing unit memory. An apparatus and a computer-implemented method may include accessing allocated graphical processing unit memory of a second resource via a link from a first resource. The allocated graphical processing unit memory may be mapped into one or more page tables of a central processing unit. A virtual address of the graphical processing unit memory from the one or more page tables of the central processing unit may be sent to the application.
    Type: Grant
    Filed: June 22, 2012
    Date of Patent: January 9, 2018
    Assignee: INTEL CORPORATION
    Inventor: Michael Apodaca
  • Publication number: 20180005345
    Abstract: Methods and apparatus relating to reducing memory latency in graphics operations are described. In an embodiment, uniform data is transferred from a buffer to a General Register File (GRF) of a processor based at least in part on information stored in a gather table. The uniform data comprises data that is uniform across a plurality of primitives in a graphics operation. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 4, 2018
    Applicant: Intel Corporation
    Inventors: Michael Apodaca, David M. Cimini, Thomas F. Raoux, Somnath Ghosh, Uddipan Mukherjee, Debraj Bose, Sthiti Deka, Yohai Gevim
  • Publication number: 20170337656
    Abstract: The same set of render commands can be re-executed for each of a plurality of tiles making up a graphic scene to be rendered. Each time the list of commands is executed, the way the commands are executed may be modified based on information received from tile pre-processing. Specifically, a jump if command may be inserted into the command list. When this command is encountered, a determination is made, based on information received from tile pre-processing pipeline, whether to execute the command for the next primitive or not. If the next primitive is to be culled then the command for the next primitive is not executed and the flow moves past that command. If the next primitive is to be executed then the jump is not implemented. This enables avoiding reloading the same list of commands over and over for every tile.
    Type: Application
    Filed: May 20, 2016
    Publication date: November 23, 2017
    Inventors: Balaji Vembu, Peter L. Doyle, Michael Apodaca, Hema C. Nalluri, Jeffery S. Boles
  • Patent number: 9747657
    Abstract: Various embodiments are presented herein that may reduce the workload of a system tasked with delivering frames of video data to a display generated by applications executing within the system. Applications executing within the system may generate new frames of video content at a specified frame rate known as frames per second (FPS). The CPU and/or GPU may be responsible for actually generating the frames at the specified FPS. These frames are then delivered to a display communicatively coupled with the system for rendering. Reducing the frame rate (FPS) may reduce the work being performed by the system because fewer frames may be generated within a given time period. This may be especially advantageous when the system is operating on battery power because it can extend the life of the battery.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: August 29, 2017
    Assignee: INTEL CORPORATION
    Inventor: Michael Apodaca
  • Publication number: 20170140572
    Abstract: A mechanism is described for facilitating efficient processing of graphics commands at computing devices. A method of embodiments, as described herein, includes detecting a current object representing a bundled state of graphics commands in a command list to be processed at a graphics processor of a computing device, and evaluating the current object to determine a previous object bound to a first set of the graphics commands, where the first set of the graphics commands is associated with a first command state corresponding to the previous object. The method may further include copying a second set of the graphics commands to a command buffer associated with the command list, where the second set of the graphics commands represents a remainder of the graphics commands in the command list upon excluding the first set of the graphics commands. The method may further include facilitating the graphics processor to execute the second set of the graphics commands from the command buffer.
    Type: Application
    Filed: November 13, 2015
    Publication date: May 18, 2017
    Applicant: INTEL CORPORATION
    Inventors: MICHAEL APODACA, SIDDHARTH Y. DHARMADHIKARI
  • Publication number: 20170091989
    Abstract: By scheduling/managing workload submission to a POSH pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: Murali Ramadoss, Balaji Vembu, Hema C. Nalluri, Michael Apodaca, Jeffery S. Boles
  • Patent number: 9601092
    Abstract: The introduction of an “out-of-memory” marker in the sorted tile geometry sequence for a tile may aid in handling out-of-memory frames. This marker allows hardware to continue rendering using the original data stream instead of the sorted data stream. This enables use of the original data stream allows the system to continue rendering without requiring any driver intervention. During the visibility generation/sorting phase, the number of memory pages required for storing the data for a rendering pass is continuously tracked. This tracking includes tracking the pages that are required even if the hardware had not run out-of-memory. This information can be monitored by a graphics driver and the driver can provide more memory pages for the system to work at full efficiency.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: March 21, 2017
    Assignee: Intel Corporation
    Inventors: Michael Apodaca, Thomas A. Piazza, Bimal Poddar
  • Patent number: 9594697
    Abstract: An apparatus and method are described for asynchronous tile-based rendering control. In one embodiment of the invention, there is a delay between when the graphics driver queues the GPU commands for rendering and when the GPU begins executing. During this delay, the graphics driver receives additional information or data about whether cache evictions may be inhibited. As such, it allows the graphics driver to defer the cache eviction control of its render cache until it has this extra information. By doing so, it reduces the memory bandwidth required for rendering 3D graphics applications and in turn reduces the power consumption of the GPU.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventor: Michael Apodaca
  • Publication number: 20160364828
    Abstract: A mechanism is described for facilitating dynamic runtime transformation of graphics processing commands for improved graphics performance on computing devices. A method of embodiments, as described herein, includes detecting a command stream associated with an application, where the command stream includes dispatches. The method may further include evaluating processing parameters relating to each of the dispatches, where evaluating further includes associating a first plan with one or more of the dispatches to transform the command stream into a transformed command stream. The method may further include associating, based on the first plan, a second plan to the one or more of the dispatches, where the second plan represents the transformed command stream. The method may further include executing the second plan, where execution of the second plan includes processing the transformed command stream in lieu of the command stream.
    Type: Application
    Filed: June 12, 2015
    Publication date: December 15, 2016
    Applicant: INTEL CORPORATION
    Inventors: James A. Valerio, Abhishek Venkatesh, Satyajit Sarangi, Michael Apodaca, Thomas F. Raoux, Hashem Hashemi, Rama S.B. Harihara
  • Publication number: 20160364829
    Abstract: A mechanism is described for facilitating efficient graphics command generation and execution for improved graphics performance at computing devices. A method of embodiments, as described herein, includes detecting an application programming interface (API) call to perform a plurality of transactions, where the API call is issued by an application at a first command buffer, where the plurality of transactions include a first set of transactions and a second set of transactions. The method may further include creating a second command buffer and appending the second command buffer to the first command buffer, where creating further includes separating the first set transactions from the second set of transactions. The method may further include executing, via the second command buffer, the first set of transactions, prior to executing the first set of transactions.
    Type: Application
    Filed: June 12, 2015
    Publication date: December 15, 2016
    Applicant: INTEL CORPORATION
    Inventors: MICHAEL APODACA, DAVID M. CIMINI
  • Publication number: 20160275920
    Abstract: The introduction of an “out-of-memory” marker in the sorted tile geometry sequence for a tile may aid in handling out-of-memory frames. This marker allows hardware to continue rendering using the original data stream instead of the sorted data stream. This enables use of the original data stream allows the system to continue rendering without requiring any driver intervention. During the visibility generation/sorting phase, the number of memory pages required for storing the data for a rendering pass is continuously tracked. This tracking includes tracking the pages that are required even if the hardware had not run out-of-memory. This information can be monitored by a graphics driver and the driver can provide more memory pages for the system to work at full efficiency.
    Type: Application
    Filed: March 19, 2015
    Publication date: September 22, 2016
    Inventors: Michael Apodaca, Thomas A. Piazza, Bimal Poddar
  • Publication number: 20160188491
    Abstract: An apparatus and method are described for asynchronous tile-based rendering control. In one embodiment of the invention, there is a delay between when the graphics driver queues the GPU commands for rendering and when the GPU begins executing. During this delay, the graphics driver receives additional information or data about whether cache evictions may be inhibited. As such, it allows the graphics driver to defer the cache eviction control of its render cache until it has this extra information. By doing so, it reduces the memory bandwidth required for rendering 3D graphics applications and in turn reduces the power consumption of the GPU.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 30, 2016
    Inventor: Michael APODACA
  • Patent number: 9355465
    Abstract: For a given texture address, a multi-mode texture sampler fetches and reduces texture data with a multi-mode filter accumulator suitable for providing a weighted average over a variety of filter footprints. A multi-mode texture sampler is configurable to provide both a wide variety of footprints and allow for a filter footprint significantly wider than the bi-linear (2×2 texel) footprint. In embodiments, filter coefficients specifying a weighting for each texel in a flexible footprint are cached from coefficient tables stored in memory. Techniques and systems are provided for dynamic allocation, update and handling of weighting coefficient tables as resources independent of sampler state.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: May 31, 2016
    Assignee: INTEL CORPORATION
    Inventors: Aleksander Olek Neyman, Michael Apodaca
  • Publication number: 20150187089
    Abstract: For a given texture address, a multi-mode texture sampler fetches and reduces texture data with a multi-mode filter accumulator suitable for providing a weighted average over a variety of filter footprints. A multi-mode texture sampler is configurable to provide both a wide variety of footprints and allow for a filter footprint significantly wider than the bi-linear (2×2 texel) footprint. In embodiments, filter coefficients specifying a weighting for each texel in a flexible footprint are cached from coefficient tables stored in memory. Techniques and systems are provided for dynamic allocation, update and handling of weighting coefficient tables as resources independent of sampler state.
    Type: Application
    Filed: December 27, 2013
    Publication date: July 2, 2015
    Inventors: Aleksander Olek Neyman, Michael Apodaca
  • Publication number: 20140354659
    Abstract: Various embodiments are presented herein that may reduce the workload of a system tasked with delivering frames of video data to a display generated by applications executing within the system. Applications executing within the system may generate new frames of video content at a specified frame rate known as frames per second (FPS). The CPU and/or GPU may be responsible for actually generating the frames at the specified FPS. These frames are then delivered to a display communicatively coupled with the system for rendering. Reducing the frame rate (FPS) may reduce the work being performed by the system because fewer frames may be generated within a given time period. This may be especially advantageous when the system is operating on battery power because it can extend the life of the battery.
    Type: Application
    Filed: November 30, 2011
    Publication date: December 4, 2014
    Inventor: Michael Apodaca
  • Publication number: 20140178047
    Abstract: Disclosed are configurations for controlling media using a chromeless media player. Gestures performed on a touch sensitive screen are used to modify the behavior of the media player. In one embodiment, a gesture recognizer recognizes a gesture performed on a touch sensitive screen. The behavior of a media player is modified based on the recognized gesture. For example, a tap gesture may toggle a playback state (play/pause) of the media player, a pinch gesture may display a seek screen, a scrub gesture may change the playback time of the media player, etc.
    Type: Application
    Filed: March 14, 2013
    Publication date: June 26, 2014
    Inventors: Thomas Michael Apodaca, Benjamin George Olander
  • Publication number: 20130342552
    Abstract: Various embodiments are presented herein that may allow an application direct access to graphical processing unit memory. An apparatus and a computer-implemented method may include accessing allocated graphical processing unit memory of a second resource via a link from a first resource. The allocated graphical processing unit memory may be mapped into one or more page tables of a central processing unit. A virtual address of the graphical processing unit memory from the one or more page tables of the central processing unit may be sent to the application.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 26, 2013
    Inventor: Michael Apodaca
  • Publication number: 20130271474
    Abstract: Various embodiments are presented herein that may reduce the workload of a GPU tasked with delivering frames of video data to a display generated by a 3D application executing within a system or computing platform. 3D applications executing within the system may generate new frames of video content at a specified frame rate known as frames per second (FPS). These frames are then delivered to a display communicatively coupled with the system for rendering. Every display has a refresh rate specified in cycles per second or Hertz (Hz). Vertical Synchronization (VSYNC) is a setting that synchronizes the frames per second (FPS) of a given application with the display's refresh rate. Forcing VSYNC on the application while the system is operating on battery power may reduce the workload on the GPU when the FPS is greater than the refresh rate resulting in greater battery life.
    Type: Application
    Filed: November 30, 2011
    Publication date: October 17, 2013
    Inventor: Michael Apodaca