Abstract: A processor core includes multiple execution units, such as a first execution unit and a second execution unit. The first execution unit may include a first functional component that supports a superscalar pipeline. The second execution unit may include a second functional component supporting a scalar pipeline. The processor core may operate in a high-performance mode by using the first execution unit and powering down the second execution unit and operate in a low-power mode by using the second execution unit and powering down the first execution unit. The processor core may include common elements shared between the multiple execution units, such as a common instruction cache, data cache, register file(s), and more.

Abstract: A method and system for a coherence protocol for buffer memories which covers interventions in multiprocessor data processing units, wherein a bus coupler maps the coherence protocol of a system bus onto a local bus and, in the event that an intervention relates to a buffer line which is in the write register, transfer this buffer line from the write register via the local bus to the intervention register.