Abstract: Programmable analog delay line devices for analog signal processing are constructed on a single integrated circuit chip using a switched capacitor storage scheme for short-term storage of the voltage or charge waveform. These devices provide variable maximum delay times without signal attenuation and with delay-to-risetime ratios of up to 102 to 103. A vector array of switched capacitor analog storage elements may be arranged in a ring-buffer topology, with the number of switched capacitor elements ranging from between about 10 and about 105. Two internal counters incremented by a common clock keep track of the variable delay between an input signal and an output signal.