Patents by Inventor Michael Hawjing Lo
Michael Hawjing Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230359373Abstract: Selective refresh techniques for memory devices are disclosed. In one aspect, a memory device that is used with an application that has frequent repeated read or write commands to certain memory segments may be able to set a flag or similar indication that exempts these certain memory segments from being actively refreshed. By exempting these memory segments from being actively refreshed, these memory segments are continuously available, thereby improving performance. Likewise, because these memory segments are so frequently the subject of a read or write command, these memory segments are indirectly refreshed through the execution of the read or write command.Type: ApplicationFiled: May 3, 2022Publication date: November 9, 2023Inventors: Engin Ipek, Hamza Omar, Bohuslav Rychlik, Saumya Ranjan Kuanr, Behnam Dashtipour, Michael Hawjing Lo, Jeffrey Gemar, Matthew Severson, George Patsilaras, Andrew Edmund Turner
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Patent number: 11662919Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.Type: GrantFiled: October 5, 2021Date of Patent: May 30, 2023Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Dexter Tamio Chun, Michael Hawjing Lo, Shyamkumar Thoziyoor, Ravindra Kumar
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Patent number: 11631450Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.Type: GrantFiled: July 16, 2021Date of Patent: April 18, 2023Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Yanru Li, Michael Hawjing Lo, Dexter Tamio Chun
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Patent number: 11372717Abstract: Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.Type: GrantFiled: July 30, 2020Date of Patent: June 28, 2022Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Michael Hawjing Lo, Dexter Tamio Chun, Xavier Loic Leloup, Laurent Rene Moll
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Patent number: 11360897Abstract: Dynamic random access memory (DRAM) data may be accessed by a memory controller using a broadcast mode or a non-broadcast mode. In the broadcast mode, a first portion of data that is the subject of an access request and a second portion of the data that is the subject of the access request may be accessed concurrently via first and second pseudo-channels, respectively. In the non-broadcast mode, data that is the subject of the access request may be accessed via a selected one of the first and second pseudo-channels.Type: GrantFiled: April 15, 2021Date of Patent: June 14, 2022Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Pankaj Deshmukh, Michael Hawjing Lo, Shyamkumar Thoziyoor
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Patent number: 11295803Abstract: Methods and apparatuses for to memories using dynamic voltage scaling are presented. The apparatus includes memory configured to communicate with a host. The memory includes a peripheral portion and a memory array. The memory is further configured to receive, from at least one power management circuit, a first supply voltage and a second supply voltage. The memory further includes a switch circuit. The switch circuit is configured to selectively provide the first supply voltage and the second supply voltage to the peripheral portion. The first supply voltage is static and has a first voltage range. The second supply voltage has a low second voltage range and a high second voltage range.Type: GrantFiled: July 31, 2020Date of Patent: April 5, 2022Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Michael Hawjing Lo, Dexter Tamio Chun, Xavier Loic Leloup, Laurent Rene Moll
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Publication number: 20220027067Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.Type: ApplicationFiled: October 5, 2021Publication date: January 27, 2022Inventors: Jungwon SUH, Dexter Tamio CHUN, Michael Hawjing LO, Shyamkumar THOZIYOOR, Ravindra KUMAR
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Patent number: 11175836Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.Type: GrantFiled: February 27, 2020Date of Patent: November 16, 2021Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Dexter Tamio Chun, Michael Hawjing Lo, Shyamkumar Thoziyoor, Ravindra Kumar
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Publication number: 20210343331Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.Type: ApplicationFiled: July 16, 2021Publication date: November 4, 2021Inventors: Jungwon SUH, Yanru LI, Michael Hawjing LO, Dexter Tamio CHUN
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Patent number: 11164618Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.Type: GrantFiled: June 19, 2020Date of Patent: November 2, 2021Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Yanru Li, Michael Hawjing Lo, Dexter Tamio Chun
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Publication number: 20210065772Abstract: Methods and apparatuses for to memories using dynamic voltage scaling are presented. The apparatus includes memory configured to communicate with a host. The memory includes a peripheral portion and a memory array. The memory is further configured to receive, from at least one power management circuit, a first supply voltage and a second supply voltage. The memory further includes a switch circuit. The switch circuit is configured to selectively provide the first supply voltage and the second supply voltage to the peripheral portion. The first supply voltage is static and has a first voltage range. The second supply voltage has a low second voltage range and a high second voltage range.Type: ApplicationFiled: July 31, 2020Publication date: March 4, 2021Inventors: Jungwon SUH, Michael Hawjing LO, Dexter Tamio CHUN, Xavier Loic LELOUP, Laurent Rene MOLL
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Publication number: 20210064463Abstract: Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.Type: ApplicationFiled: July 30, 2020Publication date: March 4, 2021Inventors: Jungwon SUH, Michael Hawjing LO, Dexter Tamio CHUN, Xavier Loic LELOUP, Laurent Rene MOLL
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Patent number: 10852809Abstract: Power saving techniques for memory systems are disclosed. In particular, exemplary aspects of the present disclosure contemplate taking advantage of patterns that may exist within memory elements and eliminating duplicative data transfers. Specifically, if data is repetitive, instead of sending the same data repeatedly, the data may be sent only a single time with instructions that cause the data to be replicated at a receiving end to restore the data to its original repeated state.Type: GrantFiled: February 6, 2019Date of Patent: December 1, 2020Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Dexter Tamio Chun, Michael Hawjing Lo
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Publication number: 20200321051Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.Type: ApplicationFiled: June 19, 2020Publication date: October 8, 2020Inventors: Jungwon SUH, Yanru LI, Michael Hawjing LO, Dexter Tamio CHUN
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Publication number: 20200278802Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.Type: ApplicationFiled: February 27, 2020Publication date: September 3, 2020Inventors: Jungwon SUH, Dexter Tamio Chun, Michael Hawjing Lo, Shyamkumar Thoziyoor, Ravindra Kumar
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Patent number: 10761774Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.Type: GrantFiled: April 3, 2018Date of Patent: September 1, 2020Assignee: Qualcomm IncorporatedInventors: Olivier Alavoine, Sejoong Lee, Tauseef Kazi, Simon Booth, Edoardo Regini, Renatas Jakushokas, Saurabh Patodia, Jeffrey Gemar, Michael Hawjing Lo, Vinod Chamarty, Boris Andreev, Tao Shen, Aravind Bhaskara, Wenbiao Wang, Stephen Molloy
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Patent number: 10726904Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.Type: GrantFiled: March 22, 2019Date of Patent: July 28, 2020Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Yanru Li, Michael Hawjing Lo, Dexter Tamio Chun
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Publication number: 20190221252Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.Type: ApplicationFiled: March 22, 2019Publication date: July 18, 2019Inventors: Jungwon SUH, Yanru LI, Michael Hawjing LO, Dexter Tamio CHUN
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Patent number: 10332582Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.Type: GrantFiled: August 2, 2017Date of Patent: June 25, 2019Assignee: QUALCOMM IncorporatedInventors: Jungwon Suh, Yanru Li, Michael Hawjing Lo, Dexter Tamio Chun
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Publication number: 20190179399Abstract: Power saving techniques for memory systems are disclosed. In particular, exemplary aspects of the present disclosure contemplate taking advantage of patterns that may exist within memory elements and eliminating duplicative data transfers. Specifically, if data is repetitive, instead of sending the same data repeatedly, the data may be sent only a single time with instructions that cause the data to be replicated at a receiving end to restore the data to its original repeated state.Type: ApplicationFiled: February 6, 2019Publication date: June 13, 2019Inventors: Jungwon Suh, Dexter Tamio Chun, Michael Hawjing Lo