Abstract: A method, system, and computer program product for bit flip aware latch placement in integrated circuit generation are provided. The method identifies a chip design for an integrated circuit. A set of chip design constraints, associated with the chip design, is identified. A set of checking groups, associated with a plurality of latches to be placed in the chip design, is determined. Based on the set of chip design constraints and the set of checking groups, a placement scheme for the plurality of latches is selected. The method places the plurality of latches within the chip design based on the placement scheme and the set of checking groups.

Abstract: A circuit comprises an antenna and a first port coupled to the antenna using a first reactive circuit. A first switching device is coupled across first and second input nodes of the first port, and configured to convey a signal across the first and second input nodes to a Near Field Communication (NFC) circuit in a first mode, and to isolate the NFC circuit from the antenna in a second mode. The antenna has a first resonance at a first frequency in a first mode and has a second resonance at a second frequency in a second mode. A second port is coupled to the antenna using a second reactive circuit. A rectifier has an input coupled to the second port and an output coupled to an energy storage device. A second switching device is coupled across the second port and configured to control an amount of current flowing through the rectifier by alternating between a first state and a second state at a third frequency when the circuit is in the second mode.

Abstract: Systems, methods, and other embodiments associated with radio frequency identification (RFID) circuits are described. According to one embodiment, a radio frequency identification circuit includes an antenna network and an integrated circuit configured to operate as a reader and a tag in combination with the antenna network. The integrated circuit is configured to provide an output admittance determined by a ratio of current and voltage negative feedback signals such that a frequency response of the combined integrated circuit and antenna network is adjustable when operating as a reader.

Abstract: Systems, methods, and other embodiments associated with radio frequency identification (RFID) circuits are described. According to one embodiment, a radio frequency identification circuit includes an antenna network and an integrated circuit configured to operate as a reader and a tag in combination with the antenna network. The integrated circuit is configured to provide an output admittance determined by a ratio of current and voltage negative feedback signals such that a frequency response of the combined integrated circuit and antenna network is adjustable when operating as a reader.

Abstract: Circuits, architectures, systems, and methods for generating temperature-stable reference voltages with offset compensation. The circuits generally include a diode junction voltage generator, and three composite voltage generators configured to operate in first and second phases or modes of operation. The diode junction voltage generator produces first and diode junction voltages with different current densities (Vd1 and Vd2). The first composite voltage (VC1) comprises at least a fraction of the first and/or second diode junction voltage. The second composite voltage (VC2) is generated during the first phase and comprises a difference between Vd2 and a sum of VC1 and an offset voltage (Ve) of an amplifier and/or other summation circuit. The third composite voltage (VC3) is generated during the second phase such that VC3 is proportional to a difference between Vd1 and a sum of Ve and VC2. A temperature-stable reference voltage proportional to VC3 may be continuously generated.

Abstract: The present invention provides shunt voltage regulation by employing a rectifying means to rectify an incoming signal and a current sinking means to divert current from the output of the rectifying means in such a way that the output voltage is maintained at an appropriate level and the modulation level does not rise above the acceptable range. This is accomplished by having two feedback mechanisms for the control of said current sinking means. A first feedback mechanism utilizes a voltage dividing means to generate a control voltage signal that will cause the average output voltage of the rectifying means to be equal to the a reference voltage. A second feedback mechanism utilizes non-linear processing means and capacitors to transmit part of the modulation frequency to the control of the current sinking means, thereby keeping the modulation at the output of the rectifying mean at an appropriate level at all time.

Abstract: In an exemplary embodiment, a system (10) is formed to include a semiconductor device (11) that is formed to function as a voltage regulator. The semiconductor device (11) is formed to have a control loop that includes an amplifier (30) and a feedback transistor (19) that provide a small signal AC gain that varies inversely to a load current of an output transistor (12) in order compensate for the manner in which the output transistor (12) transconductance depends on the load current flowing through the output transistor (12).

Abstract: The present invention provides shunt voltage regulation by employing a rectifying means to rectify an incoming signal and a current sinking means to divert current from the output of the rectifying means in such a way that the output voltage is maintained at an appropriate level and the modulation level does not rise above the acceptable range. This is accomplished by having two feedback mechanisms for the control of said current sinking means. A first feedback mechanism utilizes a voltage dividing means to generate a control voltage signal that will cause the average output voltage of the rectifying means to be equal to the a reference voltage. A second feedback mechanism utilizes non-linear processing means and capacitors to transmit part of the modulation frequency to the control of the current sinking means, thereby keeping the modulation at the output of the rectifying mean at an appropriate level at all time.

Abstract: A voltage regulator (15) utilizes a first current source (31) and a second current source (32) to form a reference current to limit current flow through an output transistor (13) during a start-up period. After the start-up period expires, the first current source (31) is disabled and the voltage regulator (15) controls the output voltage produced by the output transistor (13) instead of controlling the current flow through the output transistor (13).

Abstract: A system (10) is formed to include a semiconductor device (11) that typically is formed to function as a voltage regulator. The semiconductor device (11) is formed to have a control loop that includes an amplifier (30) and a feedback transistor (19) that provide a small signal AC gain that varies inversely to a load current of an output transistor (12) in order compensate for the manner in which the output transistor (12) transconductance depends on the load current flowing through the output transistor (12).

Abstract: A voltage regulator (15) utilizes a first current source (31) and a second current source (32) to form a reference current to limit current flow through an output transistor (13) during a start-up period. After the start-up period expires, the first current source (31) is disabled and the voltage regulator (15) controls the output voltage produced by the output transistor (13) instead of controlling the current flow through the output transistor (13).

Abstract: A current sensing circuit (50) for use in an ADSL interface circuit senses an input current (IL) flowing through a resistor (R1) and provides an image output signal at an output which is an image of the input current.

Abstract: In a telephone line interface circuit, a first transistor (Q1) is arranged in series in the signal line (3) and a second transistor (Q2) is arranged in parallel across the telephone line (3, 4), both transistors being controlled from a control circuit (5), so that, when the voltage across the telephone line falls below that required to keep the first transistor (Q1) in normal conduction, the second transistor (Q2) maintains the signal path. In order to reduce cross-over distortion, a negative feedback loop (Q5, R1, Q3, Q1) and supply voltage sensing means (6) controls the first transistor (Q1) so that it conducts only sufficient quiescent current to power the circuit, any remaining current being conducted by the second transistor (Q2), thereby maintaining both transistors in conduction down to low quiescent line current levels.

Abstract: A telephone line interface circuit has a transmit path for coupling to a telephone line and a receive path for coupling to the telephone line (2). The transmit path includes a first amplifier (A1) having an output for coupling to the line (2), a first input for receiving a signal to be transmitted and a second input for receiving a first sum signal made up of a.c. and d.c. line voltage signals plus a.c and d.c. line current signals. The feedback loop thus described has sufficient loop gain to constrain the first sum signal to be substantially equal to the signal at the first input. The receive path includes a second amplifier (A4) having a first input for receiving the first sum signal, a second input for receiving substantially twice a second sum signal made up of the a.c. and d.c. line current signals plus the d.c. line voltage signal/and an output for providing receive signals.

Abstract: A clamp circuit is described in which a video signal is capacitively coupled to an amplifier which has enabled and disabled states. An operational amplifier receives the output of the amplifier and a reference voltage and the output of the operational amplifier is fed back to the inputs of both the amplifier and the operational amplifier. The loops may be selectively disconnected and the amplifier selectively disabled so that the output of the amplifier has the same level during each of three modes namely clamp mode when the video signal is known to be black, image mode during normal operation when the video signal returns to black, and during blank mode initiated at any other desired time.

Abstract: The invention relates to a current mirror circuit (28) comprising: an input node (29); a first simple current mirror (30) of a first type, such as pnp bipolar technology, having an input coupled to said input node (29) and an output; a second simple current mirror (32) of a second semiconductor type, such as npn bipolar technology, having an input coupled to said output of said first simple current mirror and an output; a third simple current mirror (34) of said first semiconductor type having an input coupled to said output of said second simple current mirror and an output coupled to said input node (29); and an output node (31) coupled to said second simple current mirror (32) so as to receive the sum of the input and output currents of said second simple current mirror flowing in a common terminal thereof.

Abstract: A sampled data circuit having: two or more serially connected sampled data stages (2) each comprising switching means (6) and storage means (10); and clock means (4) for applying to the switching means of consecutive stages clock signals of respectively first and second phases alternating between first and second levels,characterized in thatthe clock signals also have a third level intermediate the first and second levels which is occupied simultaneously by the first and second phase clock signals.

Abstract: A circuit is disclosed for use in telephone handsets having a line signal node (1), a microphone signal input (20) and an output to an earphone amplifier. There is provided two voltage feedback loops via respective impedance networks (10, 11) and a current feedback loop (5, 7, 14). These feedback loops determine the impedance presented to the line at the signal node with specific voltage/current characteristics and signal frequencies. The first voltage feedback loop in conjunction with the current feedback loop defines the signal frequency impedance and the second voltage feedback loop defines the DC mask presented to the line.

Abstract: A switched capacitor filter includes an amplifier in a feedback or feed-forward path thereof. The amplifier (A5, C6, S7,) has a gain dependent on the ratio of stray capacitances to the capacitors used in the filter so as to compensate for errors in filter characteristics which said stray capacitances would otherwise introduce.

Abstract: A gain control cell comprises an input stage (10) having first (12) and second (13) input nodes and including a first current mirror (T.sub.14), and an output stage (11) having an output node (14) and including a second current mirror (T.sub.15). The input stage (10) is biased by a first current source I.sub.11 and the output stage (11) is biased by a second current source I.sub.12, the gain of the cell being defined by the ratio of the two current sources. The two current mirrors are matched so that errors due to the finite current gains of the current mirrors compensate for each other. The quiescent output current is thus substantially independent of the current gains of the pnp transistors used in the current mirrors.