Abstract: An arithmetic logic stage in a graphics pipeline includes a number of arithmetic logic units (ALUs). The ALUs each include, for example, a multiplier and an adder. The ALUs are interconnected by circuitry that, for example, routes the output from the multiplier in one ALU to both the adder in that ALU and an adder in another ALU.

Abstract: A method in system for latency buffered scoreboarding in a graphics pipeline of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitive to generate a plurality pixels related to the graphics primitive. An ID stored to account for an initiation of parameter evaluation for each of the plurality of pixels as the pixels are transmitted to a subsequent stage of the graphics processor. A buffer is used to store the fragment data resulting from the parameter evaluation for each of the plurality of pixels by the subsequent stage. The ID and the fragment data from the buffering are compared to determine whether they correspond to one another. The completion of parameter evaluation for each of the plurality of pixels is accounted for when the ID and the fragment data match and as the fragment data is written to a memory.

Abstract: A method for loading a shader program from system memory into GPU memory. The method includes accessing the shader program in system memory of a computer system. A DMA transfer of the shader program from system memory into GPU memory is performed such that the shader program is loaded into GPU memory in an address independent manner.

Abstract: An apparatus is disclosed. The apparatus comprises an instruction mapping table, which includes a plurality of instruction counts and a plurality of instruction pointers each corresponding with one of the instruction counts. Each instruction pointer identifies a next instruction for execution. Further, each instruction count specifies a number of instructions to execute beginning with the next instruction. The apparatus also has a data operation unit adapted to receive a data group and adapted to execute on the received data group the number of instructions specified by a current instruction count of the instruction mapping table beginning with the next instruction identified by a current instruction pointer of the instruction mapping table before proceeding with another data group.

Abstract: Data for data elements (e.g., pixels) can be stored in an addressable storage unit that can store a number of bits that is not a whole number multiple of the number of bits of data per data element. Similarly, a number of the data elements can be transferred per unit of time over a bus, where the width of the bus is not a whole number multiple of the number of bits of data per data element. Data for none of the data elements is stored in more than one of the storage units or transferred in more than one unit of time. Also, data for multiple data elements is packaged contiguously in the storage unit or across the width of the bus.

Abstract: Sourcing immediate values from a very long instruction word includes determining if a VLIW sub-instruction expansion condition exists. If the sub-instruction expansion condition exists, operation of a portion of a first arithmetic logic unit component is minimized. In addition, a part of a second arithmetic logic unit component is expanded by utilizing a block of a very long instruction word, which is normally utilized by the first arithmetic logic unit component, for the second arithmetic logic unit component if the sub-instruction expansion condition exists.

Abstract: An arithmetic logic stage in a graphics pipeline includes a number of arithmetic logic units (ALUs). The ALUs each include, for example, a multiplier and an adder. The ALUs are interconnected by circuitry that, for example, routes the output from the multiplier in one ALU to both the adder in that ALU and an adder in another ALU.

Abstract: An arithmetic logic stage in a graphics processor unit includes arithmetic logic units (ALUs) and global registers. The registers contain global values for a group of pixels. Global values may be read from any of the registers, regardless of which of the pixels is being operated on by the ALUs. However, when writing results of the ALU operations, only some of the global registers are candidates to be written to, depending on the pixel number. Accordingly, overwriting of data is prevented.

Abstract: Image-based data, such as a block of texel data, is accessed. The data includes sets of color component values. A luminance value is computed for each set of color components values, generating a range of luminance values. A first set and a second set of color component values that correspond to the minimum and maximum luminance values are selected from the sets of color component values. A third set of color component values can be mapped to an index that identifies how the color component values of the third set can be decoded using the color component values of the first and second sets. The index value is selected by determining where the luminance value for the third set lies in the range of luminance values.

Abstract: A computer-implemented graphics system has a mode of operation in which primitive coverage information is generated by a rasterizer for real sample locations and virtual sample locations for use in anti-aliasing. An individual pixel includes a single real sample location and at least one virtual sample location. If the coverage information cannot be changed by a pixel shader, then the rasterizer can write the coverage information to a framebuffer. If, however, the coverage information can be changed by the shader, then the rasterizer sends the coverage information to the shader.

Abstract: An arithmetic logic stage in a graphics pipeline includes a number of arithmetic logic units (ALUs). The ALUs each include, for example, a multiplier and an adder. The ALUs are interconnected by circuitry that, for example, routes the output from the multiplier in one ALU to both the adder in that ALU and an adder in another ALU.

Abstract: Vertex data can be accessed for a graphics primitive. The vertex data includes homogeneous coordinates for each vertex of the primitive. The homogeneous coordinates can be used to determine perspective-correct barycentric coordinates that are normalized by the area of the primitive. The normalized perspective-correct barycentric coordinates can be used to determine an interpolated value of an attribute for the pixel. These operations can be performed using adders and multipliers implemented in hardware.

Abstract: An arithmetic logic stage in a graphics processor unit pipeline includes a number of arithmetic logic units (ALUs) and at least one buffer that stores pixel data for a group of pixels. Each clock cycle, the buffer stores one row of a series of rows of pixel data. A deserializer deserializes the rows of pixel data before the pixel data is placed in the buffer. After the buffer accumulates all rows of pixel data for a pixel, then the pixel data for the pixel can be operated on by the ALUs.

Abstract: Systems and methods that decompress block compressed texture data may decompress the texture data while simplifying computations to reduce die area while maintaining the required accuracy. Reducing the die area permits more texture data to be decompressed in the same die area compared with a more accurate decompression, thereby increasing texture decompression throughput. Computations are simplified by combining denominators for linear interpolation with format conversion to decompress texture data components compressed using conventional block compression formats.

Abstract: Systems and methods for modifying the number of texture samples used to produce an anisotropically filtered texture mapped pixel may improve texture mapping performance. When the number of texture samples is reduced, fewer texels are read and fewer filtering computations are needed to produce a texture value for an anisotropic footprint. The number of texture samples is reduced based on the mip map level weight. The number of texture samples may also be modified using specific parameters for the coarse and/or fine mip map levels. The spacing between the texture samples along the major axis of anisotropy may be modified to improve image quality or texture cache performance.

Abstract: An arithmetic logic stage in a graphics processor unit pipeline includes a number of arithmetic logic units (ALUs) and at least one buffer that stores pixel data for a group of pixels. Each clock cycle, the buffer stores one row of a series of rows of pixel data. A deserializer deserializes the rows of pixel data before the pixel data is placed in the buffer. After the buffer accumulates all rows of pixel data for a pixel, then the pixel data for the pixel can be operated on by the ALUs.

Abstract: The boundary of a surface can be represented as a series of line segments. A number of polygons are successively superimposed onto the surface. The polygons utilize a common reference point and each of the polygons has an edge that coincides with one of the line segments. Coverage bits are associated with respective sample locations within a pixel. A value of a coverage bit is changed each time a sample location associated with the coverage bit is covered by one of the polygons. Final values of the coverage bits are buffered after all of the polygons have been processed. The values of the coverage bits can be used when the surface is subsequently rendered.

Abstract: In the event of a cache miss, data is written from main memory to the cache. To select a cache line to write the data to, cache lines in the cache that are not referenced during a certain interval are identified. One of the identified cache lines is selected and the data can be written to that cache line.

Abstract: Circuits, methods, and apparatus that provide texture caches and related circuits that store and retrieve texels in a fast and efficient manner. One such texture circuit provides an increased number of bilerps for each pixel in a group of pixels, particularly when trilinear or aniso filtering is needed. For trilinear filtering, texels in a first and second level of detail are retrieved for a number of pixels during a clock cycle. When aniso filtering is performed, multiple bilerps can be retrieved for each of a number of pixels during one clock cycle.

Abstract: A computer-implemented graphics system that includes a rasterizer and a shader has a mode of operation in which primitive coverage information is generated for real sample locations and virtual sample locations for use in anti-aliasing. An individual pixel includes a single real sample location and at least one virtual sample location. In some instances, a primitive may cover only virtual sample locations and does not cover a real sample location. These instances can be identified in the coverage information sent from the rasterizer to the shader, so that the shader can determine whether or not it can write color information, depth information and/or stencil information for the real sample location to a framebuffer.