Abstract: Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.

Abstract: A bus protocol compatible device includes an encoder having an input for receiving a local clock signal, and an output, a multiplexer having a first input for receiving a reference clock signal, a second input coupled to said output of said encoder, a control input for receiving a select signal, and an output, and a driver having an input coupled to said output of said multiplexer, and an output for coupling to a bus protocol link.

Abstract: A bus protocol compatible device includes an encoder having an input for receiving a local clock signal, and an output, a multiplexer having a first input for receiving a reference clock signal, a second input coupled to said output of said encoder, a control input for receiving a select signal, and an output, and a driver having an input coupled to said output of said multiplexer, and an output for coupling to a bus protocol link.

Abstract: A bus protocol compatible device, includes a transmitter having a first mode for providing a reference clock signal to an output, and a second mode for providing a training sequence to the output, and a power state controller for placing the transmitter in the first mode for a first period of time in response to a change in a link state, and in the second mode after an expiration of the first period of time.

Abstract: A bus protocol compatible device, includes a transmitter having a first mode for providing a reference clock signal to an output, and a second mode for providing a training sequence to the output, and a power state controller for placing the transmitter in the first mode for a first period of time in response to a change in a link state, and in the second mode after an expiration of the first period of time.

Abstract: Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.

Abstract: Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.

Abstract: Techniques are disclosed relating to detecting and minimizing timing problems created by clock domain crossing (CDC) in integrated circuits. In various embodiments, one or more timing parameters are associated with a path that crosses between clock domains in an integrated circuit, where the one or more timing parameters specify a propagation delay for the path. In one embodiment, the timing parameters may be distributed to different design stages using a configuration file. In some embodiments, the one or more parameters may be used in conjunction with an RTL model to simulate propagation of a data signal along the path. In some embodiments, the one or more parameters may be used in conjunction with a netlist to create a physical design for the integrated circuit, where the physical design includes a representation of the path that has the specified propagation delay.

Abstract: To vigorously test synchronization logic and protocols in a digital circuit design, a synchronization logic model uses randomization to emulate the uncertainty in synchronization clock delay time exhibited in actual circuits. The synchronization logic model is inserted into a software description of the design so that simulation will reveal faulty assumptions in the synchronization protocol. Additionally, where a non-synchronized signal crosses from one clock domain to another clock domain in an asynchronous digital design, a transition on the non-synchronized signal triggers an “X” value window on the signal for a selected period relative to the receiving clock period, so that simulation will fail if the receiving logic samples the signal value during the “X” value window. These techniques aid in effective testing of the design.

Abstract: A data transfer device for transferring packets of data across an asynchronous boundary separating a first time domain from a second time domain, and, a method for transferring the packets of data is disclosed. The device comprises a plurality of transmitter/receiver combinations, which form a plurality of channels across the asynchronous boundary, such that multiple packets of data can be transferred across the asynchronous boundary at any one time. The device comprises ordering units which preserve the order of the packets of data as they are transferred across the asynchronous boundary. The ordering units perform this function by transmitting the packets of data through transmitters in a predetermined transmitter sequence and receiving the packets of data on the receivers in a predetermined receiver sequence which corresponds to the predetermined transmitter sequence. In this way, the predetermined order of the packets of data being transferred across the asynchronous boundary is preserved.

Abstract: A bi-directional transfer device for transferring packets of data across an asynchronos boundary separating a first time domain includes control logic which utilizes a single handshake signal to both request that the first time domain receive a packet of data from the second time domain, and, acknowledge receipt of an immediately previous packet of data by the second time domain from the first time domain. The device is bi-directional in that for each packet of data sent from one time domain, a corresponding packet of data should then be received from the other time domain. If one time domain has several more packets of data to send than the other time domain, the time domain with fewer packets of data sends invalid packets of data and asserts a signal indicating that the packets of data are invalid. The device is expandable such that two or more packets of data can be simultaneously exchanged across the asynchronous boundary.

Abstract: An apparatus and method implementing an algorithm for determining the most likely least recently used cache line in a cache so that this cache line can be written back to main memory. This algorithm is implemented on a bus control unit bridging a 50 Mhz multi-processor interconnect bus with a 33 Mhz peripheral component interconnect bus through an asynchronous interface. All data being transferred between the multi-processor interconnect bus and the peripheral component interconnect bus must pass through the input/output cache on the bus control unit. The algorithm determines a unique locating path to the last used cache lines and from this determines a unique locating path to a memory location which likely contains a least recently used cache line which can then be written back to main memory. Each memory location is identified by a unique locating path which passes through a nodal tree.