Patents by Inventor Michael James Callahan, Jr.

Michael James Callahan, Jr. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8248747
    Abstract: A bi-directional protection circuit employs a single comparator for detecting fault conditions. Diodes are coupled between a detection node and voltage dividers setting references for inverting and non-inverting comparator inputs, each diode forward biased during one of the positive and negative halves of the alternating current input signal cycle and coupling the detection node to a respective one of the inverting and non-inverting comparator inputs, and reverse biased during the other of the positive and negative halves and decoupling the detection node from the other of the inverting and non-inverting comparator inputs. Upon an overcurrent condition during the positive half, a voltage at the inverting comparator input is drawn above the reference voltage at the non-inverting input. Upon an overcurrent condition during the negative half, a voltage at the non-inverting comparator input is drawn below the reference voltage at the inverting input.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: August 21, 2012
    Assignee: STMicroelectronics Co., Inc.
    Inventor: Michael James Callahan, Jr.
  • Publication number: 20100165527
    Abstract: A bi-directional protection circuit employs a single comparator for detecting fault conditions. Diodes are coupled between a detection node and voltage dividers setting references for inverting and non-inverting comparator inputs, each diode forward biased during one of the positive and negative halves of the alternating current input signal cycle and coupling the detection node to a respective one of the inverting and non-inverting comparator inputs, and reverse biased during the other of the positive and negative halves and decoupling the detection node from the other of the inverting and non-inverting comparator inputs. Upon an overcurrent condition during the positive half, a voltage at the inverting comparator input is drawn above the reference voltage at the non-inverting input. Upon an overcurrent condition during the negative half, a voltage at the non-inverting comparator input is drawn below the reference voltage at the inverting input.
    Type: Application
    Filed: November 30, 2009
    Publication date: July 1, 2010
    Applicant: STMicroelectronics, Inc.
    Inventor: Michael James Callahan, JR.
  • Patent number: 6043687
    Abstract: A precision analog circuit ensures precision matching between two or more resistive elements. In order that the two or more resistive elements are truly matched, a first electrical value, such as V.sub.DS, of the two or more resistive elements are equal and a second electrical value, such as V.sub.GS, of the two or more resistive elements are equal so that a ratio of the first resistive element to the second resistive element is a predetermined value regardless of the voltage coefficients of the resistive elements.
    Type: Grant
    Filed: July 29, 1998
    Date of Patent: March 28, 2000
    Assignee: STMicroelectronics, Inc.
    Inventor: Michael James Callahan, Jr.
  • Patent number: 4061886
    Abstract: A dual-tone multiple frequency signal generator is provided for use with telecommunications systems, data transfer systems and other applications. The tone encoding system utilizes MOS/LSI integrated circuitry on a single chip powered directly by telephone line voltages. An electronic keyboard circuit provides synchronized pulses to decode single-pole, single-throw keyboard switches by row and column. A crystal-controlled oscillator generates a reference frequency which is divided according to the row and column of an activated keyboard switch to obtain two pulse signals having frequencies representative of the activated switch. The outputs of the divider circuitry are fed to programmed logic array which generates two digitally coded signals each representing a sinusoidal waveform. A digital-to-analog ladder network converts the digitally coded signals to continuous sine waves, and an operational amplifier combines the sinusoidal waveforms to provide a dual-tone output.
    Type: Grant
    Filed: September 29, 1975
    Date of Patent: December 6, 1977
    Assignee: Mostek Corporation
    Inventors: Michael James Callahan, Jr., Gordon Bates Hoffman