Abstract: A method for network access of remote memory directly from a local instruction stream using conventional loads and stores. In cases where network IO access (a network phase) cannot overlap a compute phase, a direct network access from the instruction stream greatly decreases latency in CPU processing. The network is treated as yet another memory that can be directly read from, or written to, by the CPU. Network access can be done directly from the instruction stream using regular loads and stores. Example scenarios where synchronous network access can be beneficial are SHMEM (symmetric hierarchical memory access) usages (where the program directly reads/writes remote memory), and scenarios where part of system memory (for example DDR) can reside over a network and made accessible by demand to different CPUs.

Abstract: A method for memory access is applied in a cluster of computers linked by a network. For a given computer, a respective physical memory range is defined including a local memory range within the local RAM of the given computer and a remote memory range allocated to the given compute within the local RAM of at least one other computer in the cluster, which is accessible via the network using the network interface controllers of the computers. When a memory operation is requested at a given address in the respective physical memory range, the operation is executed on the data in the local RAM of the given computer when the data at the given address are valid in the local memory range. Otherwise the data are fetched from the given address in the remote memory range to the local memory range before executing the operation on the data.

Abstract: Provided herein are compositions comprising eicosapentaenoic acid (EPA) and polar lipids (e.g., glycolipids and phospholipids), and which do not contain any docosahexaenoic acid (DHA) or esterified fatty acids.

Abstract: A method for congestion control includes receiving at a destination computer a packet transmitted on a given flow, in accordance with a predefined transport protocol, through a network by a transmitting network interface controller (NIC) of a source computer, and marked by an element in the network with a forward congestion notification. Upon receiving the marked packet in a receiving NIC of the destination computer, a congestion notification packet (CNP) indicating a flow to be throttled is immediately queued for transmission from the receiving NIC through the network to the source computer. Upon receiving the CNP in the transmitting NIC, transmission of further packets on at least the flow indicated by the CNP from the transmitting NIC to the network is immediately throttled, and an indication of the given flow is passed from the transmitting NIC to a protocol processing software stack running on the source computer.

Abstract: A switch in a data network is configured to mediate data exchanges among network elements. The apparatus further includes a processor, which organizes the network elements into a hierarchical tree having a root node network element, vertex node network elements child node network elements that include leaf node network elements. The leaf node network elements are originate aggregation data and transmit the aggregation data to respective parent vertex node network elements. The vertex node network elements combine the aggregation data from at least a portion of the child node network elements, and transmit the combined aggregation data from the vertex node network elements to parent vertex node network elements. The root node network element is operative for initiating a reduction operation on the aggregation data.

Abstract: Provided herein are compositions comprising eicosapentaenoic acid (EPA) and polar lipids (e.g., glycolipids and phospholipids), and which do not contain any docosahexaenoic acid (DHA) or esterified fatty acids.

Abstract: A network interface device includes a host interface for connection to a host processor having a memory. A network interface is configured to transmit and receive data packets over a data network, which supports multiple tenant networks overlaid on the data network. Processing circuitry is configured to receive, via the host interface, a work item submitted by a virtual machine running on the host processor, and to identify, responsively to the work item, a tenant network over which the virtual machine is authorized to communicate, wherein the work item specifies a message to be sent to a tenant destination address. The processing circuitry generates, in response to the work item, a data packet containing an encapsulation header that is associated with the tenant network, and to transmit the data packet over the data network to at least one data network address corresponding to the specified tenant destination address.

Abstract: A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration.

Abstract: A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration.

Abstract: A method for communication in a packet data network including a subnet containing multiple nodes having respective ports. The method includes assigning respective local identifiers to the ports in the subnet, such that each port receives a respective local identifier that is unique within the subnet to serve as an address for traffic within the subnet that is directed to the port. In addition to the local identifiers, respective port identifiers are assigned to the ports, such that at least one of the port identifiers is shared by a plurality of the ports, but not by all the ports, in the subnet. The plurality of the ports are addressed collectively using the at least one of the port identifiers.

Abstract: A method for communication includes receiving a packet at a first node for transmission over a link to a second node. The data in the packet is divided into a sequence of cells of a predetermined data size. The cells have respective sequence numbers. The cells are transmitted in sequence over the link, while storing the transmitted cells in a buffer at the first node. The first node receives acknowledgments indicating the respective sequence numbers of the transmitted cells that were received at the second node. Upon receiving an indication at the first node that a transmitted cell having a given sequence number was not properly received at the second node, the stored cells are retransmitted from the buffer starting from the cell with the given sequence number.

Abstract: A method for memory access includes maintaining in a host memory, under control of a host operating system running on a central processing unit (CPU), respective address translation tables for multiple processes executed by the CPU. Upon receiving, in a peripheral device, a work item that is associated with a given process, having a respective address translation table in the host memory, and specifies a virtual memory address, the peripheral device translates the virtual memory address into a physical memory address by accessing the respective address translation table of the given process in the host memory. The work item is executed in the peripheral device by accessing data at the physical memory address in the host memory.

Abstract: A method in a system that includes first and second devices that communicate with one another over a fabric that operates in accordance with a fabric address space, and in which the second device accesses a local memory via a local connection and not over the fabric, includes sending from the first device to a translation agent (TA) a translation request that specifies an untranslated address in an address space according to which the first device operates, for directly accessing the local memory of the second device. A translation response that specifies a respective translated address in the fabric address space, which the first device is to use instead of the untranslated address is received by the first device. The local memory of the second device is directly accessed by the first device over the fabric by converting the untranslated address to the translated address.

Abstract: A method for memory access is applied in a cluster of computers linked by a network. For a given computer, a respective physical memory range is defined including a local memory range within the local RAM of the given computer and a remote memory range allocated to the given compute within the local RAM of at least one other computer in the cluster, which is accessible via the network using the network interface controllers of the computers. When a memory operation is requested at a given address in the respective physical memory range, the operation is executed on the data in the local RAM of the given computer when the data at the given address are valid in the local memory range. Otherwise the data are fetched from the given address in the remote memory range to the local memory range before executing the operation on the data.

Abstract: Remote transactions using transactional memory are carried out over a data network between an initiator host and a remote target. The transaction comprises a plurality of input-output (IO) operations between an initiator network interface controller and a target network interface controller. The IO operations are controlled by the initiator network interface controller and the target network interface controller to cause the first process to perform accesses to the memory location atomically.

Abstract: A network interface device includes a host interface for connection to a host processor and a network interface, which is configured to transmit and receive data packets over a network, and which comprises multiple distinct physical ports configured for connection to the network. Processing circuitry is configured to receive, via one of the physical ports, a data packet from the network and to decide, responsively to a destination identifier in the packet, whether to deliver a payload of the data packet to the host processor via the host interface or to forward the data packet to the network via another one of the physical ports.

Abstract: A method for communication includes allocating in a memory of a host device a contiguous, cyclical set of buffers for use by a transport service instance on a network interface controller (NIC). First and second indices point respectively to a first buffer in the set to which the NIC is to write and a second buffer in the set from which a client process running on the host device is to read. Upon receiving at the NIC a message directed to the transport service instance and containing data to be pushed to the memory, the data are written to the first buffer that is pointed to by the first index, and the first index is advanced cyclically through the set. The second index is advanced cyclically through the set when the data in the second buffer have been read by the client process.

Abstract: A data storage system includes a storage server, including non-volatile memory (NVM) and a server network interface controller (NIC), which couples the storage server to a network. A host computer includes a host central processing unit (CPU), a host memory and a host NIC, which couples the host computer to the network. The host computer runs a driver program that is configured to receive, from processes running on the host computer, commands in accordance with a protocol defined for accessing local storage devices connected to a peripheral component interface bus of the host computer, and upon receiving a storage access command in accordance with the protocol, to initiate a remote direct memory access (RDMA) operation to be performed by the host and server NICs so as to execute on the storage server, via the network, a storage transaction specified by the command.

Abstract: A method for data storage includes configuring a driver program on a host computer to receive commands in accordance with a protocol defined for accessing local storage devices connected to a peripheral component interface bus of the host computer. When the driver program receives, from an application program running on the host computer a storage access command in accordance with the protocol, specifying a storage transaction, a remote direct memory access (RDMA) operation is performed by a network interface controller (NIC) connected to the host computer so as to execute the storage transaction via a network on a remote storage device.

Abstract: A method for network access of remote memory directly from a local instruction stream using conventional loads and stores. In cases where network IO access (a network phase) cannot overlap a compute phase, a direct network access from the instruction stream greatly decreases latency in CPU processing. The network is treated as yet another memory that can be directly read from, or written to, by the CPU. Network access can be done directly from the instruction stream using regular loads and stores. Example scenarios where synchronous network access can be beneficial are SHMEM (symmetric hierarchical memory access) usages (where the program directly reads/writes remote memory), and scenarios where part of system memory (for example DDR) can reside over a network and made accessible by demand to different CPUs.