Patents by Inventor Michael L. Golden

Michael L. Golden has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230004185
    Abstract: Methods and apparatuses control electrical current supplied to a plurality of processing units in a multi-processor system. A plurality of current usage information corresponding to the processing units are received by a controller to determine a threshold current for each of the processing units. The controller determines a frequency reduction action and an instructions-per-cycle (IPC) reduction action for the each of the processing units based on the threshold current and regulates operations of the processing units based on the determined frequency and IPC reduction actions.
    Type: Application
    Filed: September 8, 2022
    Publication date: January 5, 2023
    Inventors: AMITABH MEHRA, RICHARD MARTIN BORN, SRIRAM SRINIVASAN, SNEHA KOMATIREDDY, MICHAEL L. GOLDEN, XIUTING KALEEN C. MAN, GOKUL SUBRAMANI RAMALINGAM LAKSHMI DEVI, XIAOJIE HE
  • Publication number: 20220413584
    Abstract: Methods and systems for facilitating improved power consumption control of a plurality of processing cores are disclosed. The methods improve the power consumption control by performing power throttling based on a determined excess power consumption. The methods include the steps of: monitoring using at least one event count component in the respective processing core a plurality of distributed events; calculating an accumulated weighted sum of the distributed events from the event count component; determining an excess power consumption by comparing the accumulated weighted sum with a threshold power value; and adjusting power consumption of the respective processing core based on the determined excess power consumption.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Inventors: Richard Martin Born, Gokul Subramani Ramalingam Lakshmi Devi, Michael L. Golden, Larry D. Hewitt
  • Publication number: 20220330968
    Abstract: Exemplary embodiments of the present disclosure relate to devices, systems, and methods for tissue resection in a body lumen of a patient, and may include an elongate body having a cavity at a distal end and a tissue retractor extendable distally from the distal end of the elongate body. The tissue retractor may include an expansion mechanism. The expansion mechanism may include a plurality of arms each having a first end coupled around a distal cap and expandable radially outward from the distal cap such that an anchoring mechanism on a second end of the arms is engageable with selected tissue for resection of the body lumen. The tissue resection device may further include a tissue resecting device.
    Type: Application
    Filed: July 6, 2022
    Publication date: October 20, 2022
    Applicant: BOSTON SCIENTIFIC SCIMED, INC.
    Inventors: John B. Golden, Chris Jicka, Austin Grant Johnson, Caleb A. Valdes, Serena Scott, Michael Killion Ford, Kyle P. Moore, Janice Courtois, Prashanth Somasundaram, Christopher A. Olmeda, Katie Olmeda, Michael Matthew Borek, Micah Flock, Julianne Grainger, Rachel Marie Williams, Morgan Zhu, Ryan V. Wales, Kevin L. Bagley, Scott E. Brechbiel, Alexander Joseph Burnham, Shaun Dennis Comee, Tara Ann Jarobski, Nicholas J. Mazzola, Christopher Kiyonao Oto, Rachael Campion, Danny Shu-Huan Lee
  • Patent number: 11460879
    Abstract: Methods and apparatuses control electrical current supplied to a plurality of processing units in a multi-processor system. A plurality of current usage information corresponding to the processing units are received by a controller to determine a threshold current for each of the processing units. The controller determines a frequency reduction action and an instructions-per-cycle (IPC) reduction action for the each of the processing units based on the threshold current and regulates operations of the processing units based on the determined frequency and IPC reduction actions.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: October 4, 2022
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Amitabh Mehra, Richard Martin Born, Sriram Srinivasan, Sneha Komatireddy, Michael L. Golden, Xiuting Kaleen C. Man, Gokul Subramani Ramalingam Lakshmi Devi, Xiaojie He
  • Patent number: 11419624
    Abstract: Exemplary embodiments of the present disclosure relate to devices, systems, and methods for tissue resection in a body lumen of a patient, and may include a body extending along an axis and a distal cap positioned distally of the body and coupled to a shaft extending along the axis. The body and the distal cap may be movable relative to each other. An anchoring mechanism may be capable of engaging the body and the distal cap proximate a selected tissue for resection in the body lumen. A tissue capture device may be deployable from the tissue resection device such that a selected tissue for resection is securable by the tissue capture device. The tissue resection device may further include a tissue resecting device for resecting the selected tissue for resection.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: August 23, 2022
    Assignee: BOSTON SCIENTIFIC SCIMED, INC.
    Inventors: Michael M. Borek, Micah Flock, Julianne Grainger, Christopher A. Olmeda, Katie Olmeda, Rachel M. Williams, Morgan Zhu, John B. Golden, Chris Jicka, Austin G. Johnson, Caleb A. Valdes, Serena Scott, Michael K. Ford, Kyle P. Moore, Janice Courtois, Prashanth Somasundaram, Ryan V. Wales, Scott E. Brechbiel, Rachael Campion, Tara A. Jarobski, Danny S. Lee, Alexander J. Burnham, Christopher K. Oto, Nicholas J. Mazzola, Kevin L. Bagley, Shaun D. Comee
  • Patent number: 10956332
    Abstract: A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: March 23, 2021
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: William L. Walker, Michael L. Golden, Marius Evers
  • Publication number: 20210056031
    Abstract: A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.
    Type: Application
    Filed: November 6, 2020
    Publication date: February 25, 2021
    Inventors: William L. WALKER, Michael L. GOLDEN, Marius EVERS
  • Publication number: 20190129853
    Abstract: A processor core associated with a first cache initiates entry into a powered-down state. In response, information representing a set of entries of the first cache are stored in a retention region that receives a retention voltage while the processor core is in a powered-down state. Information indicating one or more invalidated entries of the set of entries is also stored in the retention region. In response to the processor core initiating exit from the powered-down state, entries of the first cache are restored using the stored information representing the entries and the stored information indicating the at least one invalidated entry.
    Type: Application
    Filed: November 1, 2017
    Publication date: May 2, 2019
    Inventors: William L. WALKER, Michael L. GOLDEN, Marius EVERS
  • Publication number: 20120144393
    Abstract: A method and apparatus for scheduling execution of instructions in a multi-issue processor. The apparatus includes post wake logic circuitry configured to track a plurality of entries corresponding to a plurality of instructions to be scheduled. Each instruction has at least one associated source address and a destination address. The post wake logic circuitry is configured to drive a ready input indicating an entry that is ready for execution based on a current match input. A picker circuitry is configured to pick an instruction for execution based the ready input. A compare circuit is configured to determine the destination address for the picked instruction, compare the destination address to the source address for all entries and drive the current match input.
    Type: Application
    Filed: December 1, 2010
    Publication date: June 7, 2012
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: James Vinh, Kyle S. Viau, Michael L. Golden, Ganesh Venkataramanan
  • Patent number: 7472224
    Abstract: In one embodiment, a processing node includes a first processor core and a second processor core. The first processor core includes a first cache memory, such as an L2 cache, for example. The second processor core includes a second cache memory, such as an L2 cache memory. The processing node further includes a configuration unit that is coupled to the first processor core and the second processor core. The configuration unit may selectably disable portions of the first and the second cache memories.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: December 30, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Richard E. Klass, Michael L. Golden
  • Patent number: 7257678
    Abstract: In one embodiment, a processing node includes a plurality of processor cores each including a cache memory coupled to a cache monitor unit and to a configuration unit. Each cache monitor unit may be configured to independently monitor a current utilization of the cache memory to which it is coupled and to determine whether the current utilization is below a predetermined utilization value. The configuration unit may selectably disable one or more portions of the cache memory in response to the cache monitor unit determining that the current utilization is below the predetermined utilization value.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: August 14, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael L. Golden, Richard E. Klass