Patents by Inventor Michael P. Greenberg

Michael P. Greenberg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7062578
    Abstract: A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices.
    Type: Grant
    Filed: October 15, 2001
    Date of Patent: June 13, 2006
    Assignee: Acuity Imaging, LLC
    Inventors: David C. Davies, Michael P. Greenberg, Michael J. Wilt, John E. Agapakis
  • Publication number: 20020019924
    Abstract: A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices.
    Type: Application
    Filed: October 15, 2001
    Publication date: February 14, 2002
    Applicant: Acuity Imaging, LLC
    Inventors: David C. Davies, Michael P. Greenberg, Michael J. Wilt, John E. Agapakis
  • Patent number: 6308234
    Abstract: A flexible, reconfigurable processing system architecture allows for the implementation of a variety of processing system configurations to be implemented on a single device, which is preferably a PCI bus add-in extension board with an attached daughter card attached and electrically connected thereto through a PCI Mezzanine type connector, and which is plugged into a personal computer PCI expansion slot. The architecture uses the PCI bus, for example, as the local CPU bus for an embedded processor, which not only allows for flexibility in system configuration but also allows PCI devices to be hidden from the host CPU to allow for proper system startup. The architecture further permits an embedded processing CPU to be re-booted when the secondary PCI bus host bus bridge fails to respond without affecting host CPU or other secondary PCI bus peripheral devices.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: October 23, 2001
    Assignee: Acuity Imaging, LLC
    Inventors: David C. Davies, Michael P. Greenberg, Michael J. Wilt, John E. Agapakis
  • Patent number: 5977994
    Abstract: A data resampler for a data processing system for logically adjacent data samples is provided. The data resampler includes a memory subsystem for storing samples to be rendered, a digital differential analyzer (DDA) for generating an interpolation corner address for a sample to be rendered and which also generates a set of interpolation fractions. The resampler also includes a fetch unit, which receives the generated interpolation corner address and generates four source addresses of samples to be fetched from the memory subsystem. A number of memory units are included in the resampler. The first memory unit is a first in, first out FIFO memory, for holding the generated interpolation fractions and for permitting the DDA and fetch unit to continue to operate during memory read latency periods. The second memory unit is also a FIFO memory and is used to hold pixel data.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: November 2, 1999
    Assignee: Acuity Imaging, LLC
    Inventors: Michael P. Greenberg, Michael J. Wilt
  • Patent number: 4581762
    Abstract: A vision inspection system operable with foreground illumination provides user identification of selected regions of a known object for later comparison to an unknown object. A gray scale pixel array of each selected region is processed for edges and this processed data array is stored as a template for each region. Gray scale illumination data from larger corresponding areas of the unknown object are processed for edges to form gradient maps. The first template is iteratively compared to the first gradient map. A correlation value greater than a threshold value causes the system to examine the second and possibly third gradient maps on the unknown object. Distance and angular relationships of the regions are used to both identify and orient the object under test. Once the unknown object is identified and its orientation determined, various visual attributes and measurements of the object can be determined through use of visual tools.
    Type: Grant
    Filed: January 19, 1984
    Date of Patent: April 8, 1986
    Assignee: Itran Corporation
    Inventors: Stanley N. Lapidus, Joseph J. Dziezanowski, Seymour A. Friedel, Michael P. Greenberg
  • Patent number: 3944984
    Abstract: A miniaturized computer controller system utilizes reprogrammable "read only" ultraviolet memory chips instead of conventional core memories to store a control program comprising variable information regarding all electrical elements in all electrical circuit lines of the controller. The memory chips are reprogrammable within the controller and thus delicate removal of the chips for reprogramming is eliminated. The controller utilizes a central processor removably interfitting with a reprogramming module that also communicates with a programming panel.When in a "monitor" mode, the programming panel, in conjunction with the reprogramming module, allows the operator to view any particular electrical circuit line while the controller is operating. A scroll switch on the programming panel further allows the operator to view sequentially higher or lower numbered electrical circuit lines while a trace switch provides for examining any electrical circuit line to which a currently viewed element is referenced.
    Type: Grant
    Filed: April 23, 1974
    Date of Patent: March 16, 1976
    Assignee: Modicon Corporation
    Inventors: Richard E. Morley, Michael P. Greenberg