Patents by Inventor Michael RIZZOLO

Michael RIZZOLO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180114752
    Abstract: A method of forming a skip-via, including, forming a first dielectric layer on a first metallization layer, forming a second metallization layer on the first dielectric layer and a second dielectric layer on the second metallization layer, removing a section of the second dielectric layer to form a via to the second metallization layer, removing a portion of the second metallization layer to form an aperture, and removing an additional portion of the second metallization layer to form an exclusion zone.
    Type: Application
    Filed: February 7, 2017
    Publication date: April 26, 2018
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Publication number: 20180108508
    Abstract: A field emission transistor includes a gate, a fold over emitter, and fold over collector. The emitter and the collector are separated from the gate by a void and are separated from a gate contact by gate contact dielectric. The void may be a vacuum, ambient air, or a gas. Respective ends of the emitter and the collector are separated by a gap. Electrons are drawn across gap from the emitter to the collector by an electrostatic field created when a voltage is applied to the gate. The emitter and collector include a first conductive portion substantially parallel with gate and a second conductive portion substantially perpendicular with gate. The second conductive portion may be formed by bending a segment of the first conductive portion. The second conductive portion is folded inward from the first conductive portion towards the gate. Respective second conductive portions are generally aligned.
    Type: Application
    Filed: December 6, 2017
    Publication date: April 19, 2018
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo
  • Patent number: 9941088
    Abstract: A field emission transistor includes a gate, a fold over emitter, and fold over collector. The emitter and the collector are separated from the gate by a void and are separated from a gate contact by gate contact dielectric. The void may be a vacuum, ambient air, or a gas. Respective ends of the emitter and the collector are separated by a gap. Electrons are drawn across gap from the emitter to the collector by an electrostatic field created when a voltage is applied to the gate. The emitter and collector include a first conductive portion substantially parallel with gate and a second conductive portion substantially perpendicular with gate. The second conductive portion may be formed by bending a segment of the first conductive portion. The second conductive portion is folded inward from the first conductive portion towards the gate. Respective second conductive portions are generally aligned.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo
  • Patent number: 9941211
    Abstract: Methods are provided for fabricating metallic interconnect structures having reduced electrical resistivity that is obtained by applying mechanical strain to the metallic interconnect structures, as well as semiconductor structures having metallic interconnect structures formed with permanent mechanical strain to provide reduced electrical resistivity. For example, a method includes forming a metallic interconnect structure in an interlevel dielectric (ILD) layer of a back-end-of-line (BEOL) structure of a semiconductor structure, and forming a stress layer in contact with the metallic interconnect structure. A thermal anneal process is performed to cause the stress layer to expand and apply compressive strain to the metallic interconnect structure and permanently deform at least a portion of the metallic interconnect structure into a stress memorized state of compressive strain.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Nicholas A. Lanzillo, Michael Rizzolo, Theodorus E. Standaert
  • Patent number: 9941134
    Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in die narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: April 10, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Jay W. Strane
  • Publication number: 20180090372
    Abstract: A method for forming trenches of an interconnect network in a substrate. The method includes forming a first trench in the substrate, which has a first width. The method also includes forming a second trench in the substrate, which has a second width that is greater than the first width. The method also includes depositing a metal layer into the trenches, applying a dielectric over the metal, and diffusing metal atoms from the trenches to the dielectric. The dielectric absorbs a majority of the metal atoms from the first trench while simultaneously absorbing only a minority of metal atoms from the second trench.
    Type: Application
    Filed: February 16, 2017
    Publication date: March 29, 2018
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Patent number: 9929088
    Abstract: A method for via alignment includes forming first airgaps between interconnect structures and depositing a pinch off layer to close off openings to the first airgaps. A protection layer is formed in divots in the pinch off layer. The protection layer and the pinch off layer are planarized to form a surface where the protection layer remains in the divots. An interlevel dielectric layer (ILD) is deposited on the surface. The ILD and the pinch off layer are etched using the protection layer as an etch stop to align a via and expose the interconnect structure through the via.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: March 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Christopher J. Penny, Michael Rizzolo
  • Publication number: 20180082885
    Abstract: A conductive line structure comprises a first conductive line arranged in a first dielectric layer, a second conductive line arranged in the first dielectric layer, a cap layer arranged on the first conductive line and the second conductive line, and an airgap arranged between the first conductive line and the second conductive line, the airgap defined by the first dielectric layer and the cap layer.
    Type: Application
    Filed: November 30, 2017
    Publication date: March 22, 2018
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Publication number: 20180081425
    Abstract: A computer-implemented method includes tracking, using a computer processor, a position of a receiver in real space. A set of images is generated, using the computer processor, where the set of images represents a position of the receiver in virtual space, and where the position of the receiver in virtual space corresponds to the position of the receiver in real space. The set of images is transmitted, using a light fidelity (LiFi) communication system, to a display.
    Type: Application
    Filed: September 20, 2016
    Publication date: March 22, 2018
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Michael Rizzolo, Aldis G. Sipolins
  • Publication number: 20180076035
    Abstract: Multi-angled deposition and masking techniques are provided to enable custom trimming and selective removal of spacers that are used for patterning features at sub-lithographic dimensions. For example, a method includes forming a sacrificial mandrel on a substrate, and forming first and second spacers on opposing sidewalls of the sacrificial mandrel. The first and second spacers are formed with an initial thickness TS. A first angle deposition process is performed to deposit a material (e.g., insulating material or metallic material) at a first deposition angle A1 to form a first trim mask layer on an upper portion of the first spacer and the sacrificial mandrel while preventing the material from being deposited on the second spacer. A spacer etch process is performed to trim the first spacer to a first thickness T1, which is less than TS, using the first trim mask layer as an etch mask.
    Type: Application
    Filed: November 13, 2017
    Publication date: March 15, 2018
    Inventors: Marc A. Bergendahl, Sean D. Burns, Lawrence A. Clevenger, Christopher J. Penny, Michael Rizzolo
  • Publication number: 20180076034
    Abstract: Multi-angled deposition and masking techniques are provided to enable custom trimming and selective removal of spacers that are used for patterning features at sub-lithographic dimensions. For example, a method includes forming a sacrificial mandrel on a substrate, and forming first and second spacers on opposing sidewalls of the sacrificial mandrel. The first and second spacers are formed with an initial thickness Ts. A first angle deposition process is performed to deposit a material (e.g., insulating material or metallic material) at a first deposition angle A1 to form a first trim mask layer on an upper portion of the first spacer and the sacrificial mandrel while preventing the material from being deposited on the second spacer. A spacer etch process is performed to trim the first spacer to a first thickness T1, which is less than Ts, using the first trim mask layer as an etch mask.
    Type: Application
    Filed: November 13, 2017
    Publication date: March 15, 2018
    Inventors: Marc A. Bergendahl, Sean D. Burns, Lawrence A. Clevenger, Christopher J. Penny, Michael Rizzolo
  • Publication number: 20180076033
    Abstract: Multi-angled deposition and masking techniques are provided to enable custom trimming and selective removal of spacers that are used for patterning features at sub-lithographic dimensions. For example, a method includes forming a sacrificial mandrel on a substrate, and forming first and second spacers on opposing sidewalls of the sacrificial mandrel. The first and second spacers are formed with an initial thickness TS. A first angle deposition process is performed to deposit a material (e.g., insulating material or metallic material) at a first deposition angle A1 to form a first trim mask layer on an upper portion of the first spacer and the sacrificial mandrel while preventing the material from being deposited on the second spacer. A spacer etch process is performed to trim the first spacer to a first thickness T1, which is less than TS, using the first trim mask layer as an etch mask.
    Type: Application
    Filed: September 9, 2016
    Publication date: March 15, 2018
    Inventors: Marc A. Bergendahl, Sean D. Burns, Lawrence A. Clevenger, Christopher J. Penny, Michael Rizzolo
  • Patent number: 9917137
    Abstract: A method is presented for forming a semiconductor structure. The method includes depositing a barrier layer, such as a tantalum nitride (TaN) layer, over a dielectric incorporating magnetic random access memory (MRAM) regions, forming magnetic tunnel junction (MTJ) stacks over portions of the TaN layer, patterning and encapsulating the MTJ stacks, forming spacers adjacent the MTJ stacks, and laterally etching sections of the TaN layer, after spacer formation, to form an electrode under the MTJ stacks. The electrode protects the MRAM regions. The electrode can be recessed from the spacers.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Michael Rizzolo, Theodorus E. Standaert
  • Patent number: 9911651
    Abstract: A method of forming a skip-via, including, forming a first dielectric layer on a first metallization layer, forming a second metallization layer on the first dielectric layer and a second dielectric layer on the second metallization layer, removing a section of the second dielectric layer to form a via to the second metallization layer, removing a portion of the second metallization layer to form an aperture, and removing an additional portion of the second metallization layer to form an exclusion zone.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: March 6, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Publication number: 20180056862
    Abstract: Techniques are provided for alerting drivers of hazardous driving conditions using the sensing capabilities of wearable mobile technology. In one aspect, a method for alerting drivers of hazardous driving conditions includes the steps of: collecting real-time data from a driver of a vehicle, wherein the data is collected via a mobile device worn by the driver; determining whether the real-time data indicates that a hazardous driving condition exists; providing feedback to the driver if the real-time data indicates that a hazardous driving condition exists, and continuing to collect data from the driver in real-time if the real-time data indicates that a hazardous driving condition does not exist. The real-time data may also be collected and used to learn characteristics of the driver. These characteristics can be compared with the data being collected to help determine, in real-time, whether the driving behavior is normal and whether a hazardous driving condition exists.
    Type: Application
    Filed: August 21, 2017
    Publication date: March 1, 2018
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Leigh Anne H. Clevenger, Jonathan H. Connell, II, Nalini K. Ratha, Michael Rizzolo
  • Publication number: 20180061704
    Abstract: A method of forming an interconnect that in one embodiment includes forming an opening in a dielectric layer, and treating a dielectric surface of the opening in the dielectric layer with a nitridation treatment to convert the dielectric surface to a nitrided surface. The method may further include depositing a tantalum containing layer on the nitrided surface. In some embodiments, the method further includes depositing a metal fill material on the tantalum containing layer. The interconnect formed may include a nitrided dielectric surface, a tantalum and nitrogen alloyed interface that is present on the nitrided dielectric surface, a tantalum layer on the tantalum and nitrogen alloy interface, and a copper fill.
    Type: Application
    Filed: September 1, 2016
    Publication date: March 1, 2018
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • Publication number: 20180061705
    Abstract: A method of forming an interconnect that in one embodiment includes forming an opening in a dielectric layer, and treating a dielectric surface of the opening in the dielectric layer with a nitridation treatment to convert the dielectric surface to a nitrided surface. The method may further include depositing a tantalum containing layer on the nitrided surface. In some embodiments, the method further includes depositing a metal fill material on the tantalum containing layer. The interconnect formed may include a nitrided dielectric surface, a tantalum and nitrogen alloyed interface that is present on the nitrided dielectric surface, a tantalum layer on the tantalum and nitrogen alloy interface, and a copper fill.
    Type: Application
    Filed: October 13, 2017
    Publication date: March 1, 2018
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 9905459
    Abstract: A method of forming an interconnect that in one embodiment includes forming an opening in a dielectric layer, and treating a dielectric surface of the opening in the dielectric layer with a nitridation treatment to convert the dielectric surface to a nitrided surface. The method may further include depositing a tantalum containing layer on the nitrided surface. In some embodiments, the method further includes depositing a metal fill material on the tantalum containing layer. The interconnect formed may include a nitrided dielectric surface, a tantalum and nitrogen alloyed interface that is present on the nitrided dielectric surface, a tantalum layer on the tantalum and nitrogen alloy interface, and a copper fill.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: February 27, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Michael Rizzolo, Chih-Chao Yang
  • Patent number: 9899256
    Abstract: A conductive line structure comprises a first conductive line arranged in a first dielectric layer, a second conductive line arranged in the first dielectric layer, a cap layer arranged on the first conductive line and the second conductive line, and an airgap arranged between the first conductive line and the second conductive line, the airgap defined by the first dielectric layer and the cap layer.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: February 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. Deprospo, Huai Huang, Christopher J. Penny, Michael Rizzolo
  • Patent number: 9899338
    Abstract: Methods for enhancing mechanical strength of back-end-of-line (BEOL) dielectrics to prevent crack propagation within interconnect stacks are provided. After forming interconnect structures in a dielectric material layer, a pore filling material is introduced into pores of a portion of the dielectric material layer that is located in a crack stop region present around a periphery of a chip region. By filling the pores of the portion of the dielectric material layer located in the crack stop region, the mechanical strength of the dielectric material layer is selectively enhanced in the crack stop region.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: February 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Benjamin D. Briggs, Lawrence A. Clevenger, Bartlet H. DeProspo, Huai Huang, Christopher J. Penny, Michael Rizzolo